Title:
Phase noise improvement techniques for mixed-mode phase-locked loops in nanometer CMOS
Phase noise improvement techniques for mixed-mode phase-locked loops in nanometer CMOS
| dc.contributor.advisor | Kenney, J. Stevenson | |
| dc.contributor.author | Caram Wigdorsky, Juan Pablo | |
| dc.contributor.committeeMember | Ralph, Stephen E. | |
| dc.contributor.committeeMember | Durgin, Gregory D. | |
| dc.contributor.committeeMember | Causey, Richard T. | |
| dc.contributor.committeeMember | Kohl, Paul A. | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.date.accessioned | 2020-01-14T14:40:33Z | |
| dc.date.available | 2020-01-14T14:40:33Z | |
| dc.date.created | 2018-12 | |
| dc.date.issued | 2018-11-13 | |
| dc.date.submitted | December 2018 | |
| dc.date.updated | 2020-01-14T14:40:33Z | |
| dc.description.abstract | This research presents circuit-level solutions for frequency synthesis and other time-domain signal processing problems. Specifically, the proposed techniques allow for lower phase noise in phase-locked loops (PLLs) and facilitate the implementation of predominantly digital PLLs in nanometer CMOS. Three circuit architectures are proposed. The first is a hybrid digital and analog PLL architecture that is capable of suppressing reference and VCO phase noise simultaneously. The approach allows for applications in which a clean, low-noise tone must be recovered from a noisy or highly-modulated input. The second is a VCO architecture that eases tradeoffs between ring VCOs and LC VCOs. The technique reveals a high correlation between theory and measurements and provides a clear path to improving phase-noise in ring-VCO-based PLLs. The third is a time-to-digital converter (TDC) which, by the use of harmonics in ring oscillators, achieves the first reported sample-and-hold mechanism for TDCs, dynamic element matching, and quantization noise scrambling. These properties allow for the reduction of quantization noise by oversampling without loss of bandwidth. These proposed circuits, techniques and architectures, along with the experimental findings provide actionable tools for improvement of timing accuracy beyond existing techniques and further research opportunities. | |
| dc.description.degree | Ph.D. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/62182 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | Phase noise | |
| dc.subject | Jitter | |
| dc.subject | Phase-locked loops | |
| dc.subject | Oscillators | |
| dc.subject | Time-to-digital converters | |
| dc.subject | Mixed-signal circuits | |
| dc.title | Phase noise improvement techniques for mixed-mode phase-locked loops in nanometer CMOS | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Kenney, J. Stevenson | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | e0074b91-92d4-43f9-aedd-88ca7c59971d | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
| thesis.degree.level | Doctoral |