Title:
Modeling, Design and Demonstration of 1 µm Wide Low Resistance Panel Redistribution Layer Technology for High Performance Computing Applications
Modeling, Design and Demonstration of 1 µm Wide Low Resistance Panel Redistribution Layer Technology for High Performance Computing Applications
| dc.contributor.advisor | Tummala, Rao R. | |
| dc.contributor.author | Deprospo, Bartlet | |
| dc.contributor.committeeMember | Kohl, Paul | |
| dc.contributor.committeeMember | Arana, Leonel | |
| dc.contributor.committeeMember | Naeemi, Azad | |
| dc.contributor.committeeMember | Losego, Mark | |
| dc.contributor.committeeMember | Swaminathan, Madhavan | |
| dc.contributor.department | Materials Science and Engineering | |
| dc.date.accessioned | 2022-01-14T16:04:34Z | |
| dc.date.available | 2022-01-14T16:04:34Z | |
| dc.date.created | 2020-12 | |
| dc.date.issued | 2020-12-06 | |
| dc.date.submitted | December 2020 | |
| dc.date.updated | 2022-01-14T16:04:34Z | |
| dc.description.abstract | Since 2010, heterogeneous integration (HI) of multiple integrated circuits (ICs) on to a package substrate has become one of the most popular solutions to improve system performance and miniaturization. This HI has emerged to continue Moore’s Law scaling to support high performance computing (HPC) applications such as artificial intelligence, autonomous driving, 5G, cloud computing and wearable devices. Package substrate technology has only just begun to become a huge enabler to system scaling, beyond Moore’s Law, in terms of overall miniaturization, high bandwidth performance and high density of interconnections between heterogeneous dies to enable more operations per second. Redistribution layer (RDL) technology is the main component to interconnecting these ICs on a single package to scale beyond Moore’s Law. Examining RDL technology further it is observed that only back-end-of-line (BEOL) RDL fabricated on silicon can provide the interconnections needed for a high-performance system. However, this technology has reached a fundamental limitation due to the high resistance and capacitance of BEOL RDL that limits the further scaling of system performance. The objectives of this research are to address the scaling limitations of multi-layer polymer RDL down to 1µm and beyond. This research focuses on addressing these challenges by: (A) Electrical Design and Modeling of multi-layer polymer RDL for 4x lower resistance and 4x higher bandwidth than silicon BEOL RDL, (B) Design and demonstration of novel photoresist materials for scaling of polymer RDL well below 1µm using low-cost large panel-based tools and processes, (C) Fundamental evaluation of current substrate integration impacts on the novel photoresist material developed for scaling of polymer RDL, (D) Scaling of the semi-additive process (SAP) that is utilized in the panel-based RDL through fundamental material and process innovations. | |
| dc.description.degree | Ph.D. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/65999 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | HPC | |
| dc.subject | AI | |
| dc.subject | RDL | |
| dc.subject | Electronics Packaging | |
| dc.subject | Photoresist | |
| dc.subject | ||
| dc.title | Modeling, Design and Demonstration of 1 µm Wide Low Resistance Panel Redistribution Layer Technology for High Performance Computing Applications | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Tummala, Rao R. | |
| local.contributor.corporatename | School of Materials Science and Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | fe05ddb2-e957-4584-ac88-58a197df62aa | |
| relation.isOrgUnitOfPublication | 21b5a45b-0b8a-4b69-a36b-6556f8426a35 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
| thesis.degree.level | Doctoral |