Title:
Design for pre-bond testability in 3D integrated circuits
Design for pre-bond testability in 3D integrated circuits
| dc.contributor.advisor | Lee, Hsien-Hsin Sean | |
| dc.contributor.author | Lewis, Dean Leon | en_US |
| dc.contributor.committeeMember | Bakir, Muhannad | |
| dc.contributor.committeeMember | Lim, Sung Kyu | |
| dc.contributor.committeeMember | Vuduc, Richard | |
| dc.contributor.committeeMember | Yalamanchili, Sudhakar | |
| dc.contributor.department | Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2013-01-17T20:47:38Z | |
| dc.date.available | 2013-01-17T20:47:38Z | |
| dc.date.issued | 2012-08-17 | en_US |
| dc.description.abstract | In this dissertation we propose several DFT techniques specific to 3D stacked IC systems. The goal has explicitly been to create techniques that integrate easily with existing IC test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. First, we describe a general test architecture for 3D ICs. In this architecture, each tier of a 3D design is wrapped in test control logic that both manages tier test pre-bond and integrates the tier into the large test architecture post-bond. We describe a new kind of boundary scan to provide the necessary test control and observation of the partial circuits, and we propose a new design methodology for test hardcore that ensures both pre-bond functionality and post-bond optimality. We present the application of these techniques to the 3D-MAPS test vehicle, which has proven their effectiveness. Second, we extend these DFT techniques to circuit-partitioned designs. We find that boundary scan design is generally sufficient, but that some 3D designs require special DFT treatment. Most importantly, we demonstrate that the functional partitioning inherent in 3D design can potentially decrease the total test cost of verifying a circuit. Third, we present a new CAD algorithm for designing 3D test wrappers. This algorithm co-designs the pre-bond and post-bond wrappers to simultaneously minimize test time and routing cost. On average, our algorithm utilizes over 90% of the wires in both the pre-bond and post-bond wrappers. Finally, we look at the 3D vias themselves to develop a low-cost, high-volume pre-bond test methodology appropriate for production-level test. We describe the shorting probes methodology, wherein large test probes are used to contact multiple small 3D vias. This technique is an all-digital test method that integrates seamlessly into existing test flows. Our experimental results demonstrate two key facts: neither the large capacitance of the probe tips nor the process variation in the 3D vias and the probe tips significantly hinders the testability of the circuits. Taken together, this body of work defines a complete test methodology for testing 3D ICs pre-bond, eliminating one of the key hurdles to the commercialization of 3D technology. | en_US |
| dc.description.degree | PhD | en_US |
| dc.identifier.uri | http://hdl.handle.net/1853/45756 | |
| dc.publisher | Georgia Institute of Technology | en_US |
| dc.subject | Shorting probes | en_US |
| dc.subject | Test wrapper design | en_US |
| dc.subject | 3D-MAPS | en_US |
| dc.subject | DFT | en_US |
| dc.subject | Design for test | en_US |
| dc.subject | 3D integration | en_US |
| dc.subject | Pre-bond test | en_US |
| dc.subject | Test architecture | en_US |
| dc.subject.lcsh | Three-dimensional integrated circuits | |
| dc.subject.lcsh | Integrated circuits | |
| dc.title | Design for pre-bond testability in 3D integrated circuits | en_US |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 |