(Georgia Institute of Technology, 2011)
Rasquinha, Mitchelle; Hassan, Syed Minhaj; Song, William; Chae, Kwanyeob; Cho, Minki; Mukhopadhyay, Saibal; Yalamanchili, Sudhakar
3D integration with through-silicon-vias (TSVs) can
provide enormous bandwidth between processor die and memory
die. The central goal of our work is to explore the limits
of performance improvement that can be achieved with such
integration. Towards this end we propose a model of the
impact of 3D TSVs on system performance. The model leads
to several key observations i) increased miss tolerance (smaller
caches) and hence improved core scaling for a fixed die size, ii)
higher sustained IPC per core, iii) significantly smaller, energy
efficient DRAM banks, iv) redistribution of system power to
the cores and on -die interconnect, and v) TSV utilization is
a function of the relationship between reference locality and the
bandwidth properties of the intradie network. These observations
are repeated in cycle level simulations of a 64 tile architecture.
(Georgia Institute of Technology, 2009-04-10)
Cho, Minki; Sathe, Nikhil; Yalamanchili, Sudhakar; Mukhopadhyay, Saibal
This paper first presents an analysis of the global thermal field in many core processors in deep nanometer (to 16nm) nodes
under power and thermal budget. We show that the thermal field can have significant spatiotemporal non-uniformity along
with high maximum temperature. We propose spatiotemporal power multiplexing as a proactive method to reduce spatial
and temporal temperature gradients. Several power multiplexing policies are evaluated for a 256 core many-core processor
in 16nm nodes which demonstrate that the simple cyclic core-activation can achieve highly uniform thermal field with low
maximum temperature.