(Georgia Institute of Technology, 2011)
Rasquinha, Mitchelle; Hassan, Syed Minhaj; Song, William; Chae, Kwanyeob; Cho, Minki; Mukhopadhyay, Saibal; Yalamanchili, Sudhakar
3D integration with through-silicon-vias (TSVs) can
provide enormous bandwidth between processor die and memory
die. The central goal of our work is to explore the limits
of performance improvement that can be achieved with such
integration. Towards this end we propose a model of the
impact of 3D TSVs on system performance. The model leads
to several key observations i) increased miss tolerance (smaller
caches) and hence improved core scaling for a fixed die size, ii)
higher sustained IPC per core, iii) significantly smaller, energy
efficient DRAM banks, iv) redistribution of system power to
the cores and on -die interconnect, and v) TSV utilization is
a function of the relationship between reference locality and the
bandwidth properties of the intradie network. These observations
are repeated in cycle level simulations of a 64 tile architecture.