Organizational Unit:

School of Materials Science and Engineering

Permanent Link

https://hdl.handle.net/1853/70762

Parent Organization

Organizational Unit

College of Engineering

ArchiveSpace Name Record

https://finding-aids.library.gatech.edu/agents/corporate_entities/1126

Full item page

Publication Search Results

Now showing 1 - 10 of 19

Modeling, design and fabrication of substrate-embedded inductors with high inductance density and low DC resistance for integrated voltage regulators

(Georgia Institute of Technology, 2020-04-28) Suresh, Srinidhi

There is an increasing need for voltage regulators to be integrated closer to active devices such as CPUs and GPUs. These integrated voltage regulators (IVRs) provide numerous performance benefits including higher efficiency, lower parasitics, and increased functionality while miniaturizing the overall system size. However, passive components i.e. inductors, generally occupy the largest volume in power distribution networks (PDNs). Therefore, realizing high-density inductors with ultra-thin form-factors is the main bottleneck to enable highly miniaturized heterogeneous integration of IVRs. An approach that can design cores and topologies with ultra-high inductance density without increasing the real-estate by using low-cost integration processes is required to address the challenges of developing inductors for IVRs. Metal-polymer composites (MPCs)-based interleaved substrate-embedded toroid inductors can meet all the criteria. MPCs as cores for inductor packages have high permeability, high resistivity, low eddy current losses and high frequency stability. An embedded interleaved toroid inductor topology using MPC cores can provide 50% more inductance, 33% higher Q-factor for the same DC resistance compared to an embedded solenoid topology. The combination of better material properties of MPCs, with an efficient toroid topology provides very high inductance densities at smaller inductor sizes, while maintaining low losses and DC resistance. The proposed work aims to improve upon current material approaches for inductor fabrication by providing better density, reduced thickness and DC resistance in a package-integrated format. This work aims to provide a basic understanding of the performance of a single-inductor using embedded toroid approach and the properties that govern its electrical behavior which can be further be scaled to coupled/tapped inductors in next-generation systems.
Modeling, design and demonstration of large 2.5D glass BGA packages for balanced chip-and-board-level reliability

(Georgia Institute of Technology, 2017-04-28) Jayaram, Vidya

Transistor scaling, driven by Moore’s Law, has enabled the integration of billions of transistors on a single integrated chip (IC); thereby enabling rapid miniaturization of microprocessor devices such as smartphones, servers and personal computers. However, silicon integration following Moore's law is now reaching its limits due to increasing design complexity and cost, bringing the need for a new "System Scaling" approach for further miniaturization and performance improvements. The System-on-Package (SOP) approach, pioneered by Georgia Tech PRC, relies on co-integration of multiple electronic functions on a package substrate, as opposed to on-chip. Packaging, therefore, becomes key in enabling higher functional densities. An example of this new approach to system design is the recent trend of "split dies" where a large devices is broken down into smaller devices at finer I/O pitches that are interconnected on a substrate using high-density wiring. These advanced package architectures such as 2.5D interposer packages now rely on packaging to improve performance and miniaturize the system as a whole. Silicon interposers are particularly attractive in such split-die applications due to their outstanding lithographic capability enabling high-density, high-speed die-to-die interconnections. Such 2.5D interposers tend to be fairly large with body sizes exceeding 30mmx40mm, bringing unprecedented board-level reliability challenges due to large mismatch in coefficients of thermal expansion (CTE) between silicon and mother boards. These challenges are typically addressed by introducing an additional organic BGA package between interposer and board to accommodate for the CTE mismatch and decrease in pitch. However, this degrades electrical performance with longer interconnection lengths, and adds to the overall cost. Glass has emerged as an alternative substrate technology to overcome the shortcomings of silicon. Glass has been demonstrated to have superior electrical properties than silicon with lower losses and can accommodate high-density wiring owing to micron-scale lithographic design rules. Further, glass can be tailored for a wide CTE range of 3.3 to 9.8 ppm/K. This unique property brings design flexibility to address board-level reliability challenges and directly assemble large glass interposer packages to boards without the need for an intermediate organic package. The primary objective of this research is to model, design and demonstrate a large, 2.5D glass BGA package with 1) direct SMT-to-board interconnection; and 2) balanced chip- and- board-level reliability. The ultimate goal is to provide guidelines for the design of 2.5D glass BGA packages, optimizing the glass CTE to mitigate warpage and achieve system-level reliability, and subsequently the assembly process and sequence. Finite-element models were built to assess the reliability of 2.5D glass packages with direct SMT assembly to the board. The methodology for achieving balanced chip- and- board-level reliability was validated through focused modeling and experimental results for a single-chip package. Board-level reliability was recognized as the most critical challenge and enhanced by using innovative doped solder materials such as Indium’s Mn-doped SACmTM alloy and strain-relief mechanisms to give more design flexibility. Failure distribution analysis and optical characterization was performed to evaluate thermal cycling reliability. A process design approach was demonstrated for mitigating warpage induced by thermocompression bonding on ultra-thin, low- and- high-CTE substrates at I/O pitches below 50µm. By selecting optimum thermal profiles for mitigating chip-level assembly warpage, board-level assembly is enabled at larger package sizes, and system-level reliability is thereby enhanced.
Modeling, design, fabrication and reliability characterization of ultra-thin glass BGA package-to-board interconnections

(Georgia Institute of Technology, 2016-04-26) Singh, Bhupender

Recent trends to miniaturized systems such as smartphones and wearables, as well as the rise of autonomous vehicles relying on all-electric and smart in-car systems, have brought unprecedented needs for superior performance, functionality, and cost requirements. Transistor scaling alone cannot meet these metrics unless the remaining system components such as substrates and interconnections are scaled down to bridge the gap between transistor and system scaling. In this regard, 3D glass system packages have emerged as a promising alternative due to their ultra-short system interconnection lengths, higher component densities and system reliability enabled by the tailorable coefficient of thermal expansion (CTE), high dimensional stability and surface smoothness, outstanding electrical properties and low-cost panel-level processability of glass. The research objectives are to demonstrate board-level reliability of large, thin, glass packages directly mounted on PCB with conventional BGAs at pitches of 400µm SMT and smaller. Two key innovations are introduced to accomplish the objectives: a.) Reworkable circumferential polymer collars providing strain-relief at critical high stress concentration areas in the solder joints, b.) novel Mn-doped SACMTM solder to provide superior drop test performance without degrading thermomechanical reliability. Modeling, package and board design, fabrication and reliability characterization were carried out to demonstrate reliable board-level interconnections of large, ultra-thin glass packages. Finite-element modeling (FEM) was used to investigate the effectiveness of circumferential polymer collars as a strain-relief solution on fatigue performance. Experimental results with polymer collars indicated a 2X improvement in drop performance and 30% improvement in fatigue life. Failure analysis was performed using characterization techniques such as confocal surface acoustic microscopy (C-SAM), optical microscopy, X-ray imaging, and scanning electron microscopy/energy dispersive spectrometry (SEM/EDS). Model-to-experiment correlation was performed to validate the effectiveness of polymer collars as a strain-relief mechanism. Enhancement in board-level reliability performance with advances in solder materials based on Mn-doped SACMTM is demonstrated in the last part of the thesis.The studies, thus, demonstrate material, design and process innovations for package-to-board interconnection reliability with ultra-thin, large glass packages.
Polymer materials, processes, and structures for optical turning in 3D glass photonic interposers

(Georgia Institute of Technology, 2016-04-25) Vis, William A.

Increasing bandwidth demands for cloud computing and autonomous applications push the need for system scaling instead of transistor scaling as predicted by Moore’s Law. Optoelectronic interconnections have the potential to enable system scaling at higher bandwidth, power efficiency, and lower cost than copper wiring. The objective of this research is to demonstrate polymer-based optical waveguides with integrated optical turning structures in ultra-thin glass interposers, for fiber-to-chip or chip-to-chip optical interconnections. The fundamental material and process challenges associated with achieving this objective are encompassed in: (1) polymer-glass interfaces and adhesion, (2) lithographically-defined polymer waveguides, and (3) integrated turning structures by inclined lithography. Process guidelines for substrate preparation, adhesion enhancement, and lithographic precision of siloxane-based polymer waveguides in glass were established by fundamentally breaking down and optimizing each process step. In addition, a new process was demonstrated to achieve, for the first time, waveguides with integrated turning structures with self-alignment and symmetry in a single exposure. The new process was enabled by fabricating pre-existing, direct-coated, metallic masks before the inclined exposure step. The demonstrated structures were imaged by polished cross-sectioning and Scanning Electronic Microscopy (SEM).
Fine-pitch Cu-snag die-to-die and die-to-interposer interconnections using advanced slid bonding

(Georgia Institute of Technology, 2013-11-19) Honrao, Chinmay

Multi-chip integration with emerging technologies such as a 3D IC stack or 2.5D interposer is primarily enabled by the off-chip interconnections. The I/O density, speed and bandwidth requirements for emerging mobile and high-performance systems are projected to drive the interconnection pitch to less than 20 microns by 2015. A new class of low-temperature, low-pressure, high-throughput, cost-effective and maufacturable technologies are needed to enable such fine-pitch interconnections. A range of interconnection technologies are being pursued to achieve these fine-pitch interconnections, most notably direct Cu-Cu interconnections and copper pillars with solder caps. Direct Cu-Cu bonding has been a target in the semiconductor industry due to the high electrical and thermal conductivity of copper, its high current-carrying capability and compatibility with CMOS BEOL processes. However, stringent coplanarity requirements and high temperature and high pressure bonding needed for assembly have been the major barriers for this technology. Copper-solder interconnection technology has therefore become the main workhouse for off-chip interconnections, and has recently been demonstrated at pitches as low as 40 microns. However, the current interconnection approaches using copper-solder structures are not scalable to finer feature sizes due to electromigration, and reliability issues arising with decreased solder content. Solid Liquid Inter-Diffusion (SLID) bonding is a promising solution to achieve ultra-fine-pitch and ultra-short interconnections with a copper-solder system, as it relies on the conversion of the entire solder volume into thermally-stable and highly electromigration-resistant intermetallics with no residual solder. Such a complete conversion of solders to stable intermetallics, however, relies on a long assembly time or a subsequent post-annealing process. To achieve pitches lower than 30 micron pitch, this research aims to study two ultra-short copper-solder interconnection approaches: (i) copper pillar and solder cap technology, and (ii) a novel technology which will enable interconnections with improved electrical performance by fast and complete conversion of solders to stable intermetallics (IMCs) using Solid Liquid Diffusion (SLID) bonding approach. SLID bonding, being a liquid state diffusion process, combined with a novel, alternate layered copper-solder bump structure, leads to higher diffusion rates and a much faster conversion of solder to IMCs. Moreover this assembly bonding is done at a much lower temperature and pressure as compared to that used for Cu-Cu interconnections. FEM was used to study the effect of various assembly and bump-design characteristics on the post-assembly stress distribution in the ultra-short copper-solder joints, and design guidelines were evolved based on these results. Test vehicles, based on these guidelines, were designed and fabricated at 50 and 100 micron pitch for experimental analysis. The bumping process was optimized, and the effect of current density on the solder composition, bump-height non-uniformity and surface morphology of the deposited solder were studied. Ultra-short interconnections formed using the copper pillar and solder cap technology were characterized. A novel multi-layered copper-solder stack was designed based on diffusion modeling to optimize the bump stack configuration for high-throughput conversion to stable Cu3Sn intermetallic. Following this modeling, a novel bumping process with alternating copper and tin plating layers to predesigned thicknesses was then developed to fabricate the interconnection structure. Alternate layers of copper and tin were electroplated on a blanket wafer, as a first demonstration of this stack-technology. Dies with copper-solder test structures were bonded using SLID bonding to validate the formation of stable intermetallics.
Thin-film trench capacitors for silicon and organic packages

(Georgia Institute of Technology, 2011-08-29) Wang, Yushu

The continuous trend towards mega-functional, high-performance and ultra-miniaturized system has been driving the need for advances in novel materials with superior properties leading to thin components, high-density interconnect substrates and interconnections. Power supply and management is becoming a critical bottleneck for the advances in such mega-functional systems because power components do not scale down with the rest of the system resulting in bulky and stand-alone power modules. Amongst the power components, thin film capacitors are considered the most challenging to integrate because of several manufacturability concerns. The challenges are related to process compatibility of high permittivity dielectrics with substrates and high surface area electrodes, yield, leakage and losses. This thesis focuses on novel thin film capacitor technologies that address some of these critical challenges.
High-density capacitor array fabrication on silicon substrates

(Georgia Institute of Technology, 2010-11-19) Sethi, Kanika

System integration and miniaturization demands are driving integrated thin film capacitor technologies with ultra-high capacitance densities for power supply integrity and efficient power management. The emerging need for voltage conversion and noise-free power supply in bioelectronics and portable consumer products require ultra high-density capacitance of above 100 μF/cm2 with BDV 16-32 V ,independent capacitor array terminals and non-polar dielectrics. The aim of this research,therefore, is to explore a new silicon- compatible thin film nanoelectrode capacitor technology that can meet all these demands. The nanoelectrode capacitor paradigm has two unique advances. The first advance is to achieve ultra-high surface area thin film electrodes by sintering metallic particles directly on a silicon substrate at CMOS- compatible temperatures. The second advance of this study is to conformally- deposit medium permittivity dielectrics over such particulate nanoelectrodes using Atomic Layer Deposition (ALD) process. Thin film copper particle nanoelectrode with open-porous structure was achieved by choosing a suitable phosphate-ester dispersant, solvent and a sacrificial polymer for partial sintering of copper particles to provide a continuous high surface area electrode. Capacitors with conformal ALD alumina as the dielectric and Polyethylene dioxythiophene (PEDT) as the top electrode showed 30X enhancement in capacitance density for a 20-30 micron copper particulate bottom electrode and 150X enhancement of capacitance density for a 75 micron electrode. These samples were tested for their mechanical and electrical properties by using characterization techniques such as SEM, EDS, I-V and C-V plots. A capacitance density of 30 μF/cm2 was demonstrated using this approach. The technology is extensible to much higher capacitance densities with better porosity control, reduction in particle size and higher permittivity dielectrics.
Chip-last embedded low temperature interconnections with chip-first dimensions

(Georgia Institute of Technology, 2010-11-18) Choudhury, Abhishek

Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pitch and high reliability requires a fundamentally- different approach towards highly functional and integrated systems. This research demonstrates a low-profile copper-to-copper interconnect material and process approach with less than 20µm total height using adhesive bonding at lower temperature than other state-of-the-art methods. The research focuses on: (1) exploring a novel solution for ultra-fine pitch (< 30µm) interconnections, (2) advanced materials and assembly process for copper-to-copper interconnections, and (3) design, fabrication and characterization of test vehicles for reliability and failure analysis of the interconnection. This research represents the first demonstration of ultra-fine pitch Cu-to-Cu interconnection below 200°C using non-conductive film (NCF) as an adhesive to achieve bonding between silicon die and organic substrate. The fabrication process optimization and characterization of copper bumps, NCF and build-up substrate was performed as a part of the study. The test vehicles were studied for mechanical reliability performance under unbiased highly accelerated stress test (U-HAST), high temperature storage (HTS) and thermal shock test (TST). This robust interconnect scheme was also shown to perform well with different die sizes, die thicknesses and with embedded dies. A simple and reliable, low-cost and low-temperature direct Cu-Cu bonding was demonstrated offering a potential solution for future flip chip packages as well as with chip-last embedded active devices in organic substrates.
High density and high reliability thin film embedded capacitors on organic and silicon substrates

(Georgia Institute of Technology, 2008-11-20) Kumar, Manish

With the digital systems moving towards higher frequencies, lower operating voltages and higher power, supplying the required current at the right voltage and at the right time to facilitate timely switching of the CMOS circuits becomes increasingly challenging. The board level power supply cannot meet these requirements directly due to the high inductance of the package interconnections. To overcome this problem, several thin film decoupling capacitors have to be placed on the IC or close to the IC in the package. Two approaches were pursued for high-k thin film decoupling capacitors. 1) Low cost sol-gel based thin film capacitors on organic board compatible Cu-foils 2) RF-sputtered thin film capacitors on silicon substrate for silicon compatible processes While sol-gel provides cost effective technology, sputtered ferroelectric devices are more compatible from manufacturing stand point with the existing technology. Nano-crystalline barium titanate and barium strontium titanate film capacitor devices were fabricated and characterized for organic and silicon substrates respectively. Sol-gel barium titanate films were fabricated first on a bare Cu-foil and then transferred to organic board through a standard lamination process. With process optimization and film doping, a capacitance density of 3 µF/cm2 was demonstrated with breakdown voltage greater than 12V. Leakage current characteristics, breakdown voltages, and electrical reliability of the devices were significantly improved through doping of the barium titanate films and modified film chemistry. Films and interfaces were characterized with high resolution electron microscopy, SEM, XRD, and DC leakage measurements. RF sputtering was selected for ferroelectric thin film integration on silicon substrate. Barium strontium titanate (BST) films were deposited on various electrodes sputtered on silicon substrates. The main focus was to improve interface stabilities for high-k thin films on Si to yield large-area defect-free devices. Effect of bottom electrode selection and barrier layers on device yield and performance were investigated carefully. High yield and high device performance was observed for certain electrode and barrier layer combination. A capacitance density up to 1 µF/cm2 was demonstrated with a breakdown voltage above 15 V on large area, 7 mm2, devices. These two techniques can potentially meet mid-high frequency future decoupling requirements.
Thermo-mechanical reliability of ultra-thin low-loss system-on-package substrates

(Georgia Institute of Technology, 2008-11-19) Krishnan, Ganesh

Miniaturization and functionality have always governed advances in electronic system technology. To truly achieve the goal of a multi mega-functional system, advances must be made not just at the IC level, but at the system level too. This concept of tighter integration at the system level is called System-on-Package (SOP). While SOP has a wide range of applications, this work targets the mobile application space. The main driver in the mobile application space is package profile. Reduction in thickness is very critical for enabling next-generation ultra-high density mobile products. In order to pack more functionality into a smaller volume, it is absolutely imperative that package profiles are reduced. The NEMI roadmap projects that the package profile should be reduced to 200µm from the current 500µm by 2014. This work attempts to demonstrate the feasibility of ultra-thin substrates (<200µm) using a new advanced material system tailored for high-frequency mobile applications. The main barriers to adoption of thin substrates include processing challenges, concerns about via and through hole reliability and warpage. Each of these factors is studied and a full-fledged test vehicle built to demonstrate the reliability of thin substrates using the advanced low-loss RXP-4/RXP-1 material system. Finite element models are developed to provide an understanding of the factors that affect the reliability of these substrates. Finally, IC assembly is demonstrated on these substrates.