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OSP Final Research Reports

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Now showing 1 - 10 of 146
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Data staging on future platforms: Systems management for high performance and resilience

2014-05 , Schwan, Karsten , Eisenhauer, Greg S. , Wolf, Matthew

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Performance debugging support for many-core processors project

2012-09 , Prvulovic, Milos , Oh, Jungju , Park, Sunjae

In recent years, the number of cores available on a processor has increased rapidly, while the performance of an individual core has increased much more slowly. As a result, achieving a large performance improvement for applications now requires programmers to leverage the increased core count. This is often a very challenging problem, and many parallel applications end up suffering from performance bugs caused by scalability limiters. These prevent performance from improving as much as it should with more cores. Since we expect core counts to continue increasing for the foreseeable future, addressing scalability limiters is important for developing software that will obtain better performance on future hardware. This project, jointly funded by SRC and NSF, investigated software and hardware mechanisms that automate significant parts of this performance/scalability debugging effort in order to give programmers accurate and actionable feedback about the scaling limiters present in their code. Scalability limiters are mostly caused by resource-related bottlenecks and by insufficient exposed parallelism in the application. The main resource-related bottlenecks are related to excessive cache misses, while insufficient parallelism is mostly manifested as threads waiting to complete a synchronization operation such as a lock (lock contention) or a barrier (load imbalance).

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Efficient cryptography based on lattices

2012-05-09 , Peikert, Chris , Rosen, Alon , Regev, Oded , Micciancio, Daniele

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Reverse computing compiler technology

2011-09-15 , Fujimoto, Richard M. , Vulov, George

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Qameleon: Hardware/software cooperative automated tuning for heterogeneous architectures

2013-08 , Kim, Hyesoon , Vuduc, Richard

The main goal of this project is to develop a framework that simplifies programming for heterogeneous platforms. The framework consists of (i) a runtime system to generate code that partitions and schedules work among heterogeneous processors, (ii) a general automated tuning mechanism based on machine learning and (iii) performance and power modeling techniques and profiling techniques to aid code generation.

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SoD-TEAM: Teleological reasoning in adaptive software design

8/31/2012 , Goel, Ashok K. , Rugaber, Spencer

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Integrating cryptography with emerging security applications

2012-01-01 , Boldyreva, Alexandra

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A proposal for research into the Jacobians of graphs

2012-12 , Lipton, Richard J. , Shokrieh, Farbod

Our potential theory methods allow us to prove some new results about chip-firing games and to give new proofs and/or generalizations of some known results in the subject. We also show that certain ``ad-hoc'' techniques in the literature are naturally explained or unified by our approach. In particular, we characterize reduced divisors ($G$-parking functions) on graphs as the solution to an energy (or potential) minimization problem and we provide an algorithm to efficiently compute reduced divisors.

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CPATH EAE: Extending contextualized computing in multiple institutions using threads

2012-06 , Isbell, Charles L. , Biggers, Maureen S.

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Bio-Inspired Navigation

2011-12 , Dellaert, Frank , Gill, Tarandeep

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