Person:
Kohl, Paul A.

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    Fabrication of avatrel pillars on Fujitsu's quartz wafers
    (Georgia Institute of Technology, 2009-06-05) Kohl, Paul A.
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    High-Performance Chip-to-Chip Communications Using Advanced Materials and Structures
    (Georgia Institute of Technology, 2008-09-09) Kohl, Paul A. ; Spencer, Todd ; Osborn, Tyler
    The "off-chip" bandwidth is a major bottleneck causing system delays and limited throughput, especially in areas such as processor-to-memory bandwidth and processor-to-network. The ITRS cites off-chip signal bandwidth exceeding 60 GHz within 10 years. Organic substrates (i.e. chip packages or interposers) with flip-chip solder connections are the core of the first and second level of interconnect. Off-chip bandwidth is limited to several GHz due to frequency dependent attenuation, signal reflections, and crosstalk within the polymer dielectric, via structures, and I/O signal path transitions within the chip substrate and mother board. In this work, we have introduced advances in off-chip interconnect using air-isolated, coaxial links on substrates and boards to demonstrate ultra high-speed chip-to-chip and chip-to-network communications. New approaches have been found to fabricating high frequency I/O, air-and isolated coaxial links on the substrate. The materials, processes and electrical characteristics will be presented.
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    Rapid curing of positive tone photosensitive polybenzoxazole based dielectric resin by variable frequency microwave processing
    (Georgia Institute of Technology, 2006-06) Tanikella, Ravindra V. ; Sung, Taehyun ; Bidstrup-Allen, Sue Ann ; Kohl, Paul A.
    High performance polymer dielectrics such as polyimides and polybenzoxazoles are used for several applications in the semiconductor industry due to their excellent dielectric and thermomechanical properties. However, these materials require curing at high temperatures for long periods of time in order to achieve the desired properties. High temperature exposure for long periods of time can be detrimental to device characteristics and reliability. In this study, rapid low temperature curing of a positive tone photosensitive polybenzoxazole based dielectric resin by variable frequency microwave (VFM) processing was investigated. The chemical changes occurring in the film during the condensation reaction and the percent conversion achieved as a function of cure condition were monitored by Fourier transform infrared spectroscopy. The effectiveness of rapid VFM curing was studied by characterizing the optical, electrical, and thermomechanical properties of VFM cured films with thermally cured films. The thermal stability of cured films was investigated by thermal gravitational analysis (TGA) and mass spectrometry (MS) studies. The results showed that a higher percent conversion and higher thermal stability can be achieved by using VFM processing than can be obtained using conventional thermal curing at the same cure temperature. However, the complete removal of photopackage related residual products requires slow ramp rates and long cure times.
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    Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication
    (Georgia Institute of Technology, 2005-08) Mule’, Anthony V. ; Villalaz, Ricardo A. ; Joseph, Paul Jayachandran ; Naeemi, Azad ; Kohl, Paul A. ; Gaylord, Thomas K. ; Meindl, James D.
    Polylithic integration of electrical and optical interconnect technologies is presented as a solution for merging silicon CMOS and compound semiconductor optoelectronics. In contrast to monolithic and hybrid integration technologies, polylithic integration allows for the elimination of optoelectronic and integrated optic device-related processing from silicon CMOS manufacturing. Printed wiring board-level and compound semiconductor chip-level waveguides terminated with volume grating couplers facilitate bidirectional optical communication, where fiber-to-board and board-to-chip optical coupling occurs through a two-grating (or grating-to-grating) coupling path. A 27% increase in the electrical signal I/O projected by and 33% increase in the number of substrate-level electrical signal interconnect layers implied by the International Technology Roadmap for Semiconductors (ITRS) projections for the 32-nm technology generation are required to facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication. Buried air-gap channels provide for the routing of chip or board-level encapsulated air-clad waveguides for minimum crosstalk and maximum interconnect density. Optical signals routed on-board communicate with on-chip volume grating couplers embedded as part of a wafer-level batch package technology exhibiting compatible electrical and optical input/output interconnects. Measurements of grating-to-grating coupling reveal 31% coupling efficiency between two slab, nonoptimized, nonfocusing volume grating couplers.
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    Next-generation microvia and global wiring technologies for SOP
    (Georgia Institute of Technology, 2004-05) Sundaram, Venky ; Tummala, Rao R. ; Liu, Fuhan ; Kohl, Paul A. ; Li, Jun ; Bidstrup-Allen, Sue Ann ; Fukuoka, Yoshitaka
    As microsystems continue to move toward higher speed and microminiaturization, the demand for interconnection density both on the IC and the package levels increases tremendously. The 2002 ITRS roadmap update identifies the need for sub-100-µm area array pitch and data rates of 10 Gb/s in the package or board by the year 2010, requiring much finer lines and vias than the current microvias of 50 µm diameter and lines and spaces of 25 µm. After a brief description of the future need for high-density substrates, the historical evolution of microvia technologies worldwide is summarized. With the move toward highly integrated and higher performance system-on-a-package (SOP) technology, the demand for microvia wiring density in the package is increasing dramatically requiring new innovations in fine line, ultralow-loss, and ultrathin-film dielectrics. The low-cost needs of this technology are driving research in high throughput and large area processes in dielectric and conductor deposition. The third section of this paper describes in detail some of the key emerging global microvia research and development in the fabrication of microminiaturized, multifunction SOP packages including rapid curing of low-loss dielectric thin films on organic substrates, environmentally friendly high-speed electroless copper plating, ultrafine lines, and spaces down to 5 µm and low-cost stacked via structures without chemical-mechanical polishing. This paper concludes with a perspective on future directions in dielectrics and conductor materials and processes leading to ultrahigh-density and low-cost microvia technologies for build-up SOP implementation.
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    Fabrication of microchannels using polynorbornene photosensitive sacrificial materials
    (Georgia Institute of Technology, 2003-09) Wu, X. Q. ; Reed, H. A. ; Wang, Y. ; Rhodes, L. F. ; Elce, E. ; Ravikiran, R. ; Shick, R. A. ; Henderson, Clifford L. ; Allen, S. A. B. ; Kohl, Paul A.
    A processing method has been demonstrated for the fabrication of microchannels using photosensitive polynorbornene copolymer based sacrificial materials. The channel geometric patterns of sacrificial polymer were made via photolithography. The sacrificial polymer patterns were encapsulated with a dielectric medium and then thermally decomposed to form air channels. For the thermal decomposition of sacrificial polymer, the heating program was determined on the basis of the kinetic model obtained from thermogravimetric analysis to maintain the decomposition at a constant rate. The results indicate that a properly selected heating program can avoid the deformation in the channel structure; at the same conditions, a large-size channel is more easily deformed than a small one. The tapered-structure microchannels were also produced using a gray-scale mask. The result shows that a suitably low contrast for the photosensitive sacrificial material can lead to smooth and tapered microchannels.
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    Chip-to-Module Interconnections Using "Sea of Leads" Technology
    (Georgia Institute of Technology, 2003-01) Bakir, Muhannad S. ; Reed, Hollie A. ; Mulé, Anthony V. ; Jayachandran, Joseph Paul ; Kohl, Paul A. ; Martin, Kevin P. ; Gaylord, Thomas K. ; Meindl, James D.
    The drive toward higher density and higher performance in integrated circuits creates a need to keep interconnects short and eliminate layers of packaging. In this article, we propose a novel, ultrahigh-density (exceeding 10⁴leads per cm²), compliant, wafer-level, input/output interconnection technology called "sea of leads" as a key enabling technology for future high-performance microsystems. The mechanical compliance is addressed through slippery leads (leads released from the surface) and embedded air gaps.The ability to fabricate embedded air gaps has enabled the integration of optical interconnects with high index-of-refraction mismatches between the core and cladding.