(Georgia Institute of Technology, 2005-08)
Mule’, Anthony V.; Villalaz, Ricardo A.; Joseph, Paul Jayachandran; Naeemi, Azad; Kohl, Paul A.; Gaylord, Thomas K.; Meindl, James D.
Polylithic integration of electrical and optical interconnect
technologies is presented as a solution for merging silicon
CMOS and compound semiconductor optoelectronics. In contrast
to monolithic and hybrid integration technologies, polylithic integration
allows for the elimination of optoelectronic and integrated
optic device-related processing from silicon CMOS manufacturing.
Printed wiring board-level and compound semiconductor
chip-level waveguides terminated with volume grating couplers facilitate
bidirectional optical communication, where fiber-to-board
and board-to-chip optical coupling occurs through a two-grating
(or grating-to-grating) coupling path. A 27% increase in the electrical
signal I/O projected by and 33% increase in the number of
substrate-level electrical signal interconnect layers implied by the
International Technology Roadmap for Semiconductors (ITRS)
projections for the 32-nm technology generation are required to
facilitate 10 Tb/s aggregate bidirectional fiber-to-the-chip communication.
Buried air-gap channels provide for the routing of chip
or board-level encapsulated air-clad waveguides for minimum
crosstalk and maximum interconnect density. Optical signals
routed on-board communicate with on-chip volume grating couplers
embedded as part of a wafer-level batch package technology
exhibiting compatible electrical and optical input/output interconnects.
Measurements of grating-to-grating coupling reveal 31%
coupling efficiency between two slab, nonoptimized, nonfocusing
volume grating couplers.
(Georgia Institute of Technology, 2003-01)
Bakir, Muhannad S.; Reed, Hollie A.; Mulé, Anthony V.; Jayachandran, Joseph Paul; Kohl, Paul A.; Martin, Kevin P.; Gaylord, Thomas K.; Meindl, James D.
The drive toward higher density and higher performance in integrated circuits creates a need to keep interconnects short and eliminate layers of packaging. In this article, we propose a novel, ultrahigh-density (exceeding 10⁴leads per cm²), compliant, wafer-level, input/output interconnection technology called "sea of leads" as a key enabling technology for future high-performance microsystems. The mechanical compliance is addressed through slippery leads (leads released from the surface) and embedded air gaps.The ability to fabricate embedded air gaps has enabled the integration of optical interconnects with high index-of-refraction mismatches between the core and cladding.