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Daniel Guggenheim School of Aerospace Engineering

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End date: 2017 × Start date: 2017 × Item Type: Publication × search.filters.applied.f.resourcesubtype: Thesis ×

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Experimental investigation of fast plasma production for the VAIPER antenna

2017-12-11 , Chan, Cheong Yu

For this Master’s thesis, I will conduct the preliminary experimental study of fast plasma ignition times under varying conditions. The timing of the plasma needs to be characterized before a small scale plasma antenna can be completed. The experimental part of this project is a collaboration between Prof. Mitchell Walker’s High Power Electric Propulsion Lab (HPEPL) in Aerospace Engineering and Prof. Morris Cohen’s group in Electrical and Computer Engineering at the Georgia Institute of Technology.

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Evaluation of new enroute performance measures for air navigation service providers

2017-07-27 , Piquet, Helene Sophie

In a context of steady growth of air traffic world wide, Air Navigation Service Providers must meet increasing demand and report on the quality of their performance. This research presents the design and evaluation of novel performance metrics: the relevance of ATC set of standard routes, the lateral deviation and difference in length and duration between airlines filed flight plans, actual trajectories and wind optimal routes. The proposed metrics are predicated on the necessity for the metrics to be robust, easy to compute and applicable to several different Air Traffic Management Systems, eg. Europe vs USA.

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Resilient, multi-core and safety-critical computing architectures

2017-07-27 , Guillaumet, Tom

With the onset of multi-core chips, the single-core market is closing down. Those chips constitute a new challenge for aerospace and safety-critical industries in general. Little is known about the certification of software running on these systems. There is therefore a strong need for developing embedded multi-core architectures, yet compliant with safety-criticality constraints. In this thesis, a reconfigurable multi-core architecture is described. Its suitability for executing safety-critical embedded applications is discussed. It is argued that its dynamic features allow for graceful degradation of the system, and that interference channels can be mitigated if spatial partitioning is enforced on its Network on Chip (NoC). Furthermore, the problem of the allocation of applications on the architecture is formulated as an Integer Linear Programming optimization problem. An algorithm is developed to reallocate the applications running on the fabric when hardware faults occur. The proposed algorithm enforces spatial partitioning on the Network on Chip throughout the reconfigurations. It supports multiple types of NoC topologies, constraints and hardware faults. Finally, the behavior of the presented algorithm is demonstrated in several configurations and for different scenarios of degradation of the architecture. Its performance in terms of computation time is studied, and the results indicate that its use in a real-time environment is possible.

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