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School of Materials Science and Engineering

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College of Engineering

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Now showing 1 - 10 of 17

Advanced materials and processes for high-density capacitors for next-generation integrated voltage regulators

(Georgia Institute of Technology, 2019-11-11) Spurney, Robert Grant

Capacitors are key components for power conversion, delivery, and management. Along with inductors, they dictate the size and performance of voltage regulators in power distribution networks (PDNs), which convert and regulate the power that gets delivered to the increasingly power-hungry integrated circuits (ICs). When the voltage regulators are integrated into the package, referred to as integrated voltage regulators (IVRs), they provide many benefits over traditional voltage regulators, including higher power density, system miniaturization, and improved efficiency. To enable IVRs, capacitors must be integrated either on-chip or in the package, while providing high capacitance density, high frequency stability, low equivalent series resistance (ESR), and high temperature stability. Tantalum capacitors have an advantage over many other types of capacitor technologies due to their high capacitance density and high temperature stability they can provide. The tantalum nanoparticle-based anode provides an ultra-high surface area, so that high volumetric capacitance densities can be achieved. A tantalum-pentoxide dielectric can be formed directly on the anode structure to provide a high-permittivity oxide that is incredibly stable with changes in temperature. However, the high-surface area electrodes result in long electrical pathways for charge and discharge current, which results in capacitors with high equivalent series resistance (ESR) and low frequency stability. Additionally, their bulky design limits their integration capability. This research proposes, designs, and demonstrates a novel printed-tantalum thin-film capacitor design that solves many of the issues associated with traditional tantalum capacitors. The thin-film design results in capacitors with an ultra-thin form factor in thickness that can be integrated into the package. Additionally, the thin structure provides shorter pathways for the charge and discharge current, to dramatically improve the frequency stability and reduce the ESR of the capacitors, all while maintaining ultra-high capacitance density. In this thesis, a model is developed that is used to correlate the capacitor materials’ nanostructures to the bulk device properties, including capacitance density, frequency stability, and ESR. A process is then developed to fabricate the capacitors and integrate them directly on-package, while studying the relationships between process, structure, and performance. The integrated capacitors are shown to meet the performance objectives set out by this work. Finally, evaluation of the capacitor reliability is conducted. It is shown that the use of barrier layer materials can extend the high-temperature lifetime of the capacitors by limiting the diffusion of oxygen and moisture into the capacitor material system.
Modeling, design, materials, processes and reliability of multi-layer redistribution wiring layers on glass substrates for next generation of high-performance computing applications

(Georgia Institute of Technology, 2019-05-17) Nair, Chandrasekharan

There is a growing demand for high performance computing with miniaturization in many electronic systems such as servers for cloud computing, accurate weather prediction, smart mobile and wearable devices and autonomous driving cars. The development of 2.5D silicon interposers in 2010 for heterogeneous integration of graphical processing unit (GPU) to high bandwidth memory (HBM) dies addressed this demand to a certain extent. The back-end-of-line (BEOL) RDL processes in silicon interposers have reached the peak with data rate per signal trace due to the high resistance and capacitance of BEOL RDL, limiting the system bandwidth for 2.5D silicon interposers. The cost of such interposers is also high for large body size substrates (> 1200 sq. mm) due to the fabrication on wafer-based platforms and hence, such interposers have been primarily been used today for cost-insensitive applications like cloud computing. To address these limitations, panel-based organic package substrates with a vast range of body sizes (500-5000 sq.mm) have been under development. These low-cost, high performance panel-based substrates will bring down the cost of high-performance computing systems as well as introduce 2.5D interposers for consumer applications like mobile computing. However, such panel-based substrates have not been able to scale multi-layer polymer RDL below 5 µm RDL which is the primary requirement for 2.5D interposer substrates. The objectives of this research are to address the scaling limitations of multi-layer polymer RDL down to 2 µm and below. This research is focused on addressing these limitations by: (A) Modeling for layer-to-layer registration to predict the fundamental limit of capture pad required for laminate and glass core substrates (B) Design of multi-layer polymer RDL for 5X bandwidth and 3X lower latency than silicon BEOL RDL (C) Design and demonstration of novel materials and processes for scaling polymer RDL well below 2 µm using low-cost panel-based tools and processes (D) Reliability analysis of 2 µm multi-layer polymer RDL and identifying future needs for novel polymer dielectrics for scaling polymer RDL to sub 1-micron features.
Modeling, design, fabrication and characterization of miniaturized, high-current handling and high-efficiency inductors

(Georgia Institute of Technology, 2018-12-18) Sun, Teng

Analytical models were developed to design magnetic materials with desired permeability and frequency stability. Two loss mechanisms, eddy current loss and ferromagnetic resonance (FMR) loss, were included in the models to capture behaviors of magnetic materials at high frequency. Based on the models, magnetic materials were designed to have 2D flake shape for both high permeability and high-frequency stability. The accuracy of developed models were proofed by the good correlation between calculated and measured permeability data. By incorporating the designed magnetic flakes as the cores, two types of magnetic-core inductor, spiral inductors and solenoid inductors, were modeled and designed by using finite element models (FEMs) to achieve high current-handling. Furthermore, innovative substrate-compatible processes were developed to fabricate the designed magnetic-core inductors. One process named as core-less process was developed to fabricate the spiral inductors. Another process named as cavity-embedding process was developed to fabricate the solenoid inductors. Electrical characterizations were performed to measure the frequency-dependent and current-dependent inductance of fabricated inductors. A good correlation between measurement and simulation was observed, indicating the accuracy of inductor FEMs.
Reliable fine-pitch chip-to-substrate copper interconnections with high-through assembly and high power-handling

(Georgia Institute of Technology, 2018-07-27) Shahane, Ninad Makarand

The objectives of this work are to design and demonstrate novel chip-to-package substrate Cu-based interconnections without solders at 20µm pitch for power handling at current densities exceeding 10E5 A/cm2, high-throughput manufacturability, and thermomechanical reliability without cracking low-K on-chip dielectrics. To realize these objectives, two approaches are proposed, based on design of nanoscale bonding interfaces for assembly throughput, and electrical, thermal and reliability performances. The first approach utilizes novel Au-based bimetallic thin-films applied on Cu bumps and pads to prevent oxidation and enhance bonding reactivity. This approach focuses on thin-film interdiffusion in nanocrystalline Cu-Ni/Pd-Au layers and the reaction kinetics behind intermetallic compound (IMC) formation at the bonded interfaces. A high-speed thermocompression assembly process is developed and validated to boost throughput. Furthermore, the stability of these interconnection systems is demonstrated through extensive thermomechanical and electro migration reliability testing. The second approach introduces low-modulus nanocopper foam caps on bulk Cu micro-bumps to act as compliant and reactive bonding interfaces. A fundamental understanding of this sintering process is proposed and contrasted to that of conventional nanoparticle-based systems. Using co-electrodeposition techniques, patterned nano-Cu foam capped interconnections are fabricated and a first assembly of such compliant interconnections is demonstrated. In conclusion, these unique Cu interconnection technologies address cost, manufacturability, and scalability and therefore, have the potential to become the next interconnection nodes for high-performance systems.
Ultra-thin polymer dielectric materials and ultra-small via and trench processes for 20micron bump pitch re-distribution layer (RDL) structures for high density packages

(Georgia Institute of Technology, 2017-08-15) Suzuki, Yuya

Higher interconnect density between multiple chips is required because of the need of the high bandwidth data transmission for many electronic systems, such as smart mobile devices, cloud and edge computing, and in machine learning in autonomous driving and robotics. Although side-by-side integration with 2.5D silicon interposers with back end of line (BEOL) wafer processes have enabled the high input-output (I/O) density interconnections, they have challenges in electrical performance and cost. Meanwhile, organic package substrates have higher electrical performance and low cost capability, however, they have been unable to bridge the I/O pitch gap from 80 µm to 20 µm, because of the dimensional instability and warpage. The objectives of this research are to explore and demonstrate ultra-thin dry film polymer materials, processes and lithographic structures to form copper-polymer re-distribution layers (RDL) with silicon wafer-like interconnection densities, but at lower capacitance, resistance and at lower cost. This research is focused on addressing the limitations of current approaches by; (a) design and demonstration of a novel ultra-thin RDL dielectric material that satisfies the properties for RDL with scalability of conductor wiring to 2 µm by SAP, (b) investigation of an innovative embedded trench process with fly-cutting planarization tool to achieve 5 µm diameter micro-vias, and 2 µm wiring traces with high positional accuracy at ±1-2 µm. Detail design of the dielectric material was based on the 50 ohm impedance matching calculation and thermo-mechanical finite element modeling approach. Additionally, new dielectric materials with excellent properties were introduced, and in-depth analysis of their electrical, thermo-mechanical and adhesion properties were performed. To develop the RDL wiring process, a new embedded trench formation process was developed using parallel mask projection processes and an innovative planarization process to address the challenges of RDL scaling with current processes.
Modeling, design and demonstration of large 2.5D glass BGA packages for balanced chip-and-board-level reliability

(Georgia Institute of Technology, 2017-04-28) Jayaram, Vidya

Transistor scaling, driven by Moore’s Law, has enabled the integration of billions of transistors on a single integrated chip (IC); thereby enabling rapid miniaturization of microprocessor devices such as smartphones, servers and personal computers. However, silicon integration following Moore's law is now reaching its limits due to increasing design complexity and cost, bringing the need for a new "System Scaling" approach for further miniaturization and performance improvements. The System-on-Package (SOP) approach, pioneered by Georgia Tech PRC, relies on co-integration of multiple electronic functions on a package substrate, as opposed to on-chip. Packaging, therefore, becomes key in enabling higher functional densities. An example of this new approach to system design is the recent trend of "split dies" where a large devices is broken down into smaller devices at finer I/O pitches that are interconnected on a substrate using high-density wiring. These advanced package architectures such as 2.5D interposer packages now rely on packaging to improve performance and miniaturize the system as a whole. Silicon interposers are particularly attractive in such split-die applications due to their outstanding lithographic capability enabling high-density, high-speed die-to-die interconnections. Such 2.5D interposers tend to be fairly large with body sizes exceeding 30mmx40mm, bringing unprecedented board-level reliability challenges due to large mismatch in coefficients of thermal expansion (CTE) between silicon and mother boards. These challenges are typically addressed by introducing an additional organic BGA package between interposer and board to accommodate for the CTE mismatch and decrease in pitch. However, this degrades electrical performance with longer interconnection lengths, and adds to the overall cost. Glass has emerged as an alternative substrate technology to overcome the shortcomings of silicon. Glass has been demonstrated to have superior electrical properties than silicon with lower losses and can accommodate high-density wiring owing to micron-scale lithographic design rules. Further, glass can be tailored for a wide CTE range of 3.3 to 9.8 ppm/K. This unique property brings design flexibility to address board-level reliability challenges and directly assemble large glass interposer packages to boards without the need for an intermediate organic package. The primary objective of this research is to model, design and demonstrate a large, 2.5D glass BGA package with 1) direct SMT-to-board interconnection; and 2) balanced chip- and- board-level reliability. The ultimate goal is to provide guidelines for the design of 2.5D glass BGA packages, optimizing the glass CTE to mitigate warpage and achieve system-level reliability, and subsequently the assembly process and sequence. Finite-element models were built to assess the reliability of 2.5D glass packages with direct SMT assembly to the board. The methodology for achieving balanced chip- and- board-level reliability was validated through focused modeling and experimental results for a single-chip package. Board-level reliability was recognized as the most critical challenge and enhanced by using innovative doped solder materials such as Indium’s Mn-doped SACmTM alloy and strain-relief mechanisms to give more design flexibility. Failure distribution analysis and optical characterization was performed to evaluate thermal cycling reliability. A process design approach was demonstrated for mitigating warpage induced by thermocompression bonding on ultra-thin, low- and- high-CTE substrates at I/O pitches below 50µm. By selecting optimum thermal profiles for mitigating chip-level assembly warpage, board-level assembly is enabled at larger package sizes, and system-level reliability is thereby enhanced.
Modeling, design and demonstration of ultra-short, fine-pitch solder-based interconnection systems with high-throughput assembly

(Georgia Institute of Technology, 2017-03-15) Huang, Ting-Chia Nathan

Emerging high-performance computing systems have been driving the need for advanced packaging solutions such as high-density 2.5D interposer packages with escalating pitch, performance, and reliability requirements for off-chip interconnections. The objectives of this research are to design, develop and demonstrate novel, manufacturable, solder-based interconnection and assembly technologies at 20µm pitch, addressing the scalability limitations of conventional Cu pillars in terms of thermomechanical reliability, thermal stability and power-handling capability. Pitch scaling with solders is accompanied by a necessary reduction in solder volume and subsequent increase in the volumetric contribution of intermetallics, raising serious concerns for stress management and reliability. Fine control of interfacial reactions is, therefore, key in extending solder-based interconnections to finer pitches and constitutes the first challenge addressed in this thesis. Intermetallic formation is primarily governed by the assembly process and the surface metallurgy that reacts with the solder, with the specific challenges and associated research tasks defined below. From assembly perspective, pitch scaling brings a shift from conventional reflow to thermocompression bonding. Leading-edge TC-NCP (thermocompression with non-conductive paste) processes, first established by Amkor, have shown high promises for fine-pitch assembly at 40µm pitch and below. Through dynamic control of the temperature gradient in the assembled package, TC-NCP enables shorter reaction times and improved solder collapse and assembly yield. However, thermocompression processes inherently have to be customized for any given package design, with no existing guidelines for process design. A fundamental understanding of TC-NCP is, therefore, required to design thermal and force profiles that provide accurate control over the reaction. This is the objective of the first research task. Finite element modeling of the heat transfer in TC assembly considering tool – materials – package interactions was first established and validated experimentally to provide guidelines for optimization of assembly profiles. The developed methodology was applied to design the bonding profiles used to build all specimens in this thesis. This research also enabled the first demonstration of thermocompression assembly on high-density, ultra-thin glass substrates. Intermetallic growth in solder interconnection systems has also been traditionally controlled through the reacting surface metallurgy applied on the substrate pads. Over the last decade, standard ENEPIG (electroless Ni – electroless Pd – immersion Au) finish has been the metallurgy of choice in high-end applications for its outstanding reliability. However, the typically high thicknesses of Ni in ENEPIG limits its pitch scalability and degrades its high-frequency performance. Novel, Ni-free, metallic surface finishes are, therefore, required to meet the needs of emerging high-performance systems and form reliable interconnections at 20µm pitch with less than 10µm solder height. With such limited solder volume, risks of Au embrittlement and subsequent joints failure are also increased. The second research task addresses these challenges with the design of a new metallurgical system for reliable, ultra-short Cu pillar interconnections, based on the novel electroless Pd autocatalytic Au (EPAG) finish supplied by Atotech GmbH. The EPAG composition was optimized based on a comprehensive study including wettability testing, analysis of interfacial reactions, shear testing and thermal cycling. The optimal finish composition yielded a unique reaction with formation of a single intermetallic, resistant to Au embrittlement. Cu pillar assemblies with the optimized EPAG composition exhibited a 3x improvement in fatigue life compared to assemblies with standard ENEPIG with less than 10µm solder height, demonstrating potential scalability of the Cu pillar technology to 20µm pitch. With further reduction in solder volume to achieve finer pitches, the solder is expected to fully react into intermetallics, if not during chip-level assembly itself, then during subsequent process steps. Solid-liquid interdiffusion (SLID) bonding has been proposed and extensively researched as an alternative technology to form all-intermetallic joints with improved pitch scalability, power handling capability and thermal stability. However, the adoption of existing SLID technologies has been limited to date due to reliability concerns, notably related to voiding, and manufacturability and cost challenges due to low assembly throughput. This last technical challenge was addressed in the third research task with the design and demonstration of a void-free, manufacturable SLID technology. In the proposed metastable SLID technology, the Cu6Sn5 metastable phase was isolated using Ni diffusion barrier layers, enabling full conversion into void-free intermetallics with highest interdiffusion rates. Metastable SLID was demonstrated, for the first time, at pitches down to 20µm on Si and glass substrates, with superior shear strength of 90MPa, outstanding electromigration resistance at 105A/cm2, good thermal stability after 1000h high temperature storage at 200℃ and excellent thermomechanical reliability.
Modeling, design, fabrication and reliability characterization of ultra-thin glass BGA package-to-board interconnections

(Georgia Institute of Technology, 2016-04-26) Singh, Bhupender

Recent trends to miniaturized systems such as smartphones and wearables, as well as the rise of autonomous vehicles relying on all-electric and smart in-car systems, have brought unprecedented needs for superior performance, functionality, and cost requirements. Transistor scaling alone cannot meet these metrics unless the remaining system components such as substrates and interconnections are scaled down to bridge the gap between transistor and system scaling. In this regard, 3D glass system packages have emerged as a promising alternative due to their ultra-short system interconnection lengths, higher component densities and system reliability enabled by the tailorable coefficient of thermal expansion (CTE), high dimensional stability and surface smoothness, outstanding electrical properties and low-cost panel-level processability of glass. The research objectives are to demonstrate board-level reliability of large, thin, glass packages directly mounted on PCB with conventional BGAs at pitches of 400µm SMT and smaller. Two key innovations are introduced to accomplish the objectives: a.) Reworkable circumferential polymer collars providing strain-relief at critical high stress concentration areas in the solder joints, b.) novel Mn-doped SACMTM solder to provide superior drop test performance without degrading thermomechanical reliability. Modeling, package and board design, fabrication and reliability characterization were carried out to demonstrate reliable board-level interconnections of large, ultra-thin glass packages. Finite-element modeling (FEM) was used to investigate the effectiveness of circumferential polymer collars as a strain-relief solution on fatigue performance. Experimental results with polymer collars indicated a 2X improvement in drop performance and 30% improvement in fatigue life. Failure analysis was performed using characterization techniques such as confocal surface acoustic microscopy (C-SAM), optical microscopy, X-ray imaging, and scanning electron microscopy/energy dispersive spectrometry (SEM/EDS). Model-to-experiment correlation was performed to validate the effectiveness of polymer collars as a strain-relief mechanism. Enhancement in board-level reliability performance with advances in solder materials based on Mn-doped SACMTM is demonstrated in the last part of the thesis.The studies, thus, demonstrate material, design and process innovations for package-to-board interconnection reliability with ultra-thin, large glass packages.
Polymer materials, processes, and structures for optical turning in 3D glass photonic interposers

(Georgia Institute of Technology, 2016-04-25) Vis, William A.

Increasing bandwidth demands for cloud computing and autonomous applications push the need for system scaling instead of transistor scaling as predicted by Moore’s Law. Optoelectronic interconnections have the potential to enable system scaling at higher bandwidth, power efficiency, and lower cost than copper wiring. The objective of this research is to demonstrate polymer-based optical waveguides with integrated optical turning structures in ultra-thin glass interposers, for fiber-to-chip or chip-to-chip optical interconnections. The fundamental material and process challenges associated with achieving this objective are encompassed in: (1) polymer-glass interfaces and adhesion, (2) lithographically-defined polymer waveguides, and (3) integrated turning structures by inclined lithography. Process guidelines for substrate preparation, adhesion enhancement, and lithographic precision of siloxane-based polymer waveguides in glass were established by fundamentally breaking down and optimizing each process step. In addition, a new process was demonstrated to achieve, for the first time, waveguides with integrated turning structures with self-alignment and symmetry in a single exposure. The new process was enabled by fabricating pre-existing, direct-coated, metallic masks before the inclined exposure step. The demonstrated structures were imaged by polished cross-sectioning and Scanning Electronic Microscopy (SEM).
Nanoscale electrode and dielectric materials, processes and interfaces to form thin-film tantalum capacitors for high-frequency applications

(Georgia Institute of Technology, 2016-04-15) Chakraborti, Parthasarathi

Today’s thin-film passive components such as capacitors and inductors are limited to low volumetric density and large form-factors that pose as major roadblock to miniaturization of the power modules. These components are also placed far away from the IC’s leading to large interconnect parasitics and lower operating frequencies. Novel thin-film technologies with high densities and small form-factors are, therefore, required to enable miniaturization and performance at high frequencies. Glass- and silicon- based interposer technologies that utilize vertical through-via interconnections have shown way to improve power distribution network (PDN) performance with thin power-ground planes. However, integration of ultra-high density capacitors in such substrates has not yet been demonstrated. This thesis addresses these challenges with tantalum-based, silicon-integrated, ultrathin, high-density capacitors at higher operating frequencies with lower leakage properties (<0.01µA/µF). The anodization kinetics of tantalum pentoxide and the underlying leakage current mechanisms are investigated to provide optimal process guidelines. The thin-film Ta capacitors demonstrated capacitance density of 0.1 µF/mm2 at 1-10 MHz in form-factors of 50 µm, which corresponds to 6X higher volumetric density relative to commercial tantalum capacitors. An innovative approach to address incompatibility of tantalum electrodes with substrates is pursued by prefabricating the electrodes on a free-standing foil, which are then transferred onto the active wafer to form the capacitors on Si. The integration approach is designed to embed these thin tantalum capacitors on alternative substrates such as organic, glass or silicon, with copper via interconnections for lower parasitics. The thesis also explores titanium-based high-density capacitors with high-permittivity titania dielectric as a potential alternate high-density capacitor technology.