Organizational Unit:

School of Materials Science and Engineering

Permanent Link

https://hdl.handle.net/1853/70762

Parent Organization

Organizational Unit

College of Engineering

ArchiveSpace Name Record

https://finding-aids.library.gatech.edu/agents/corporate_entities/1126

Full item page

Publication Search Results

Now showing 1 - 10 of 16

Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics

(Georgia Institute of Technology, 2009-01-20) Sundaram, Venkatesh

The fundamental motivation for this dissertation is to address the widening interconnect gap between integrated circuit (IC) demands and package substrates specifically for high frequency digital-RF systems applications. Moore's law for CMOS ICs predicts that transistor density on ICs will double approximately every 18 months. The current state-of-the-art in IC package substrates is at 20µm lines/spaces and 50-60µm microvia diameter using epoxy dielectrics with loss tangent above 0.01. The research targets are to overcome the barriers of current technologies and demonstrate a set of advanced materials and process technologies capable of 5-10µm lines and spaces, and 10-30µm diameter microvias in a multilayer 3-D wiring substrate using 10-25µm thin film dielectrics with loss tangent in the <0.005. The research elements are organized as follows with a clear focus on understanding and characterization of fundamental materials structure-processing-property relationships and interfaces to achieve the next generation targets. (a) Low CTE Core Substrate, (b) Low Loss Dielectrics with 25µm and smaller microvias, (c) Sub-10µm Width Cu Conductors, and (d) Integration of the various dielectric and conductor processes.
Fatigue modeling of nano-structured chip-to-package interconnections

(Georgia Institute of Technology, 2009-01-09) Koh, Sau W.

Driven by the need for increase in system¡¯s functionality and decrease in the feature size, International Technology Roadmap for Semi-conductors has predicted that integrated chip packages will have interconnections with I/O pitch of 90 nm by the year 2018. Lead-based solder materials that have been used for many decades will not be able to satisfy the thermal mechanical requirements of these fines pitch packages. Of all the known interconnect technologies, nanostructured copper interconnects are the most promising for meeting the high performance requirements of next generation devices. However, there is a need to understand their material properties, deformation mechanisms and microstructural stability. The goal of this research is to study the mechanical strength and fatigue behavior of nanocrystalline copper using atomistic simulations and to evaluate their performance as nanostructured interconnect materials. The results from the crack growth analysis indicate that nanocrystalline copper is a suitable candidate for ultra-fine pitch interconnects applications. This study has also predicts that crack growth is a relatively small portion of the total fatigue life of interconnects under LCF conditions. The simulations result conducted on the single crystal copper nano-rods show that its main deformation mechanism is the nucleation of dislocations. In the case of nanocrystalline copper, material properties such as elastic modulus and yield strength have been found to be dependent on the grain size. Furthermore, it has been shown that there is competition between the dislocation activity and grain boundary sliding as the main deformation mode This research has shown that stress induced grain coarsening is the main reason for loss of mechanical performance of nanocrystalline copper during cyclic loading. Further, the simulation results have also shown that grain growth during fatigue loading is assisted by the dislocation activity and grain boundary migration. A fatigue model for nanostructured interconnects has been developed in this research using the above observations Lastly, simulations results have shown that addition of the antimony into nanocrystalline copper will not only increase the microstructure stability, it will also increase its strength.
High density and high reliability thin film embedded capacitors on organic and silicon substrates

(Georgia Institute of Technology, 2008-11-20) Kumar, Manish

With the digital systems moving towards higher frequencies, lower operating voltages and higher power, supplying the required current at the right voltage and at the right time to facilitate timely switching of the CMOS circuits becomes increasingly challenging. The board level power supply cannot meet these requirements directly due to the high inductance of the package interconnections. To overcome this problem, several thin film decoupling capacitors have to be placed on the IC or close to the IC in the package. Two approaches were pursued for high-k thin film decoupling capacitors. 1) Low cost sol-gel based thin film capacitors on organic board compatible Cu-foils 2) RF-sputtered thin film capacitors on silicon substrate for silicon compatible processes While sol-gel provides cost effective technology, sputtered ferroelectric devices are more compatible from manufacturing stand point with the existing technology. Nano-crystalline barium titanate and barium strontium titanate film capacitor devices were fabricated and characterized for organic and silicon substrates respectively. Sol-gel barium titanate films were fabricated first on a bare Cu-foil and then transferred to organic board through a standard lamination process. With process optimization and film doping, a capacitance density of 3 µF/cm2 was demonstrated with breakdown voltage greater than 12V. Leakage current characteristics, breakdown voltages, and electrical reliability of the devices were significantly improved through doping of the barium titanate films and modified film chemistry. Films and interfaces were characterized with high resolution electron microscopy, SEM, XRD, and DC leakage measurements. RF sputtering was selected for ferroelectric thin film integration on silicon substrate. Barium strontium titanate (BST) films were deposited on various electrodes sputtered on silicon substrates. The main focus was to improve interface stabilities for high-k thin films on Si to yield large-area defect-free devices. Effect of bottom electrode selection and barrier layers on device yield and performance were investigated carefully. High yield and high device performance was observed for certain electrode and barrier layer combination. A capacitance density up to 1 µF/cm2 was demonstrated with a breakdown voltage above 15 V on large area, 7 mm2, devices. These two techniques can potentially meet mid-high frequency future decoupling requirements.
Thermo-mechanical reliability of ultra-thin low-loss system-on-package substrates

(Georgia Institute of Technology, 2008-11-19) Krishnan, Ganesh

Miniaturization and functionality have always governed advances in electronic system technology. To truly achieve the goal of a multi mega-functional system, advances must be made not just at the IC level, but at the system level too. This concept of tighter integration at the system level is called System-on-Package (SOP). While SOP has a wide range of applications, this work targets the mobile application space. The main driver in the mobile application space is package profile. Reduction in thickness is very critical for enabling next-generation ultra-high density mobile products. In order to pack more functionality into a smaller volume, it is absolutely imperative that package profiles are reduced. The NEMI roadmap projects that the package profile should be reduced to 200µm from the current 500µm by 2014. This work attempts to demonstrate the feasibility of ultra-thin substrates (<200µm) using a new advanced material system tailored for high-frequency mobile applications. The main barriers to adoption of thin substrates include processing challenges, concerns about via and through hole reliability and warpage. Each of these factors is studied and a full-fledged test vehicle built to demonstrate the reliability of thin substrates using the advanced low-loss RXP-4/RXP-1 material system. Finite element models are developed to provide an understanding of the factors that affect the reliability of these substrates. Finally, IC assembly is demonstrated on these substrates.
Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

(Georgia Institute of Technology, 2008-03-18) Mehrotra, Gaurav

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.
Copper to copper bonding by nano interfaces for fine pitch interconnections and thermal applications

(Georgia Institute of Technology, 2008-03-06) Jha, Gopal Chandra

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law at IC level and system miniaturization with System-On-Package (SOP) paradigm at system level, have resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. However, system miniaturization poses several electrical and thermal challenges that demand innovative solutions including advanced materials, bonding and assembly techniques. Heterogeneous material and device integration for thermal structures and IC assembly are limited by the bonding technology and the electrical and thermal impedance of the bonding interfaces. Solder - based bonding technology that is prevalent today is a major limitation to future systems. The trend towards miniaturized systems is expected to drive downscaling of IC I/O pad pitches from 40µm to 1- 5µm in future. Solder technology imposes several pitch, processability and cost restrictions at such fine pitches. Furthermore, according to International Technology Roadmap for Semiconductors (ITRS-2006), the supply current in high performance microprocessors is expected to increase to 220 A by 2012. At such supply current, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer sized technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Similarly, thermal power dissipation is growing to unprecedented high with a projected power of 198 W by 2008 (ITRS 2006). Present thermal interfaces are not adequate for such high heat dissipation. Recently, copper based thin film bonding has become a promising approach to address the abovementioned challenges. However, copper-copper direct bonding without using solders has not been studied thoroughly. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. Hence, there is a need to develop a novel low temperature copper to copper bonding process. In the present study, nanomaterials - based copper-to-copper bonding is explored and developed as an alternative to solder-based bonding. To demonstrate fine pitch bonding, the patterning of these nanoparticles is crucial. Therefore, two novel self-patterning techniques based on: 1.) Selective wetting and 2.) Selective nanoparticle deposition, are developed to address this challenge. Nanoparticle active layer facilitates diffusion and, thus, a reliable bond can be achieved using less thermal budget. Quantitative characterization of the bonding revealed good metallurgical bonding with very high bond strength. This has been confirmed by several morphological and structural characterizations. A 30-micron pitch IC assembly test vehicle is used to demonstrate fine pitch patternability and bonding. In conclusion, novel nanoparticle synthesis and patterning techniques were developed and demonstrated for low-impedance and low-cost electrical and thermal interfaces.
Characterization of Nanostructured Metals and Metal Nanowires for Ultra-High Density Chip-to-Package Interconnections

(Georgia Institute of Technology, 2006-12-01) Bansal, Shubhra

Nanocrystalline materials are being explored as potential off-chip interconnects materials for next generation microelectronics packaging. Mechanical behavior and deformation mechanisms in nanocrystalline copper and nickel have been explored. Nanostructured copper interconnections exhibit better fatigue life as compared to microcrystalline copper interconnects at a pitch of 100 and #956;m and lower. Nanocrystalline copper is quite stable upto 100 oC whereas nickel is stable even up to 400 oC. Grain boundary (GB) diffusion along with grain rotation and coalescence has been identified as the grain growth mechanism. Ultimate tensile and yield strength of nanocrystalline (nc) Cu and Ni are atleast 5 times higher than microcrystalline counterparts. Considerable amount of plastic deformation has been observed and the fracture is ductile in nature. Fracture surfaces show dimples much larger than grain size and stretching between dimples indicates localized plastic deformation. Activation energies for creep are close to GB diffusion activation energies indicating GB diffusion creep. Creep rupture at 45o to the loading axis and fracture surface shows lot of voiding and ductile kind of fracture. Grain rotation and coalescence along direction of maximum resolved shear stress plays an important role during creep. Grain refinement enhances the endurance limit and hence high cycle fatigue life. However, a deteriorating effect of grain refinement has been observed on low cycle fatigue life. This is because of the ease of crack initiation in nanomaterials. Persistent slip bands (PSBs) at an angle of 45o to loading axis are observed at higher strain ranges (> 1% for nc- Cu) with a width of about 50 nm. No relationship has been observed between PSBs and crack initiation. A non-recrystallization annealing treatment, 100 oC/ 2 hrs for nc- Cu and 250 oC/ 2 hrs for nc- Ni has been shown to improve the LCF life without lowering the strength much. Fatigue crack growth resistance is higher in nc- Cu and Ni compared to their microcrystalline counterparts. This is due to crack deflection at GBs leading to a tortuous crack path. Nanomaterials exhibit higher threshold stress intensity factors and effective threshold stress intensity is proportional to the elastic modulus of the material.
Chip-Package Nano-Structured Copper and Nickel Interconnections with Metallic and Polymeric Bonding Interfaces

(Georgia Institute of Technology, 2006-11-17) Aggarwal, Ankur

With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher interconnections densities. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches. Other approaches such as compliant interconnects require lengthy connections and are limited in terms of electrical properties. A novel chip-package interconnection technology is developed to address the IC packaging requirements and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. This thesis investigates the electrical and mechanical performance of nano-structured interconnections through modeling and test vehicle fabrication. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.
Ultra-thin Ceramic Films for Low-temperature Temperature Embedding of Decoupling Capacitors into Organic Printed Wiring Boards

(Georgia Institute of Technology, 2005-10-27) Balaraman, Devarajan

As microprocessors move towards higher frequencies, lower operating voltages and higher power consumption, supplying noise-free power to the ICs becomes increasingly challenging. Decoupling capacitors with low inductance interconnections are critical to meet the power supply impedance targets. A variety of capacitors are used today to provide decoupling at different frequencies. Surface-mount multi-layer ceramic capacitors currently used at package level provide decoupling only till about 100 MHz because of the component and lead inductances. Embedding thin film capacitors into the package can expand the operating range of package level capacitors to low GHz frequencies. Thin films with capacitance of several microfarads and organic-compatible processes are required for embedding decoupling capacitors at package level. The organic-compatible high-permittivity materials available today do not provide adequate capacitance for the application on hand. While ferroelectric thin films can provide the required capacitance, processing temperatures over 300o C are required to achieve crystalline films with high permittivity. Hence, there is a need to develop novel materials and processes to integrate decoupling capacitors into currently prevalent organic packages. To this end, hydrothermal synthesis and sol-gel synthesis of BaTiO3 films were explored in this study. BaTiO3 films were synthesized by low temperature hydrothermal conversion of metallic titanium. Hydrothermal process parameters such as bath molarity and temperature were optimized to obtain thin films with grain sizes close to 100 nm, at temperatures less than 100o C. Novel post-hydrothermal treatments were developed to improve the dielectric properties of the films. Sol-gel process requires sintering at >700o C to obtain crystalline BaTiO3 films. However, the films can be synthesized on free-standing copper foils and subsequently integrated into organic packages using lamination. Prevention of foil oxidation during sintering is critical. Nickel and titanium barriers explored in this study were ineffective due to instabilities at the interfaces. Hence, films were synthesized on bare copper foils by controlling the oxygen partial pressure during sintering. Using these techniques BaTiO3 thin films with capacitances of 400 1000 nF/cm2 and breakdown voltages of 6 15 V were demonstrated. The films synthesized via either techniques exhibited stable dielectric properties up to 8 GHz owing to fine grain sizes.
New Carbon-Silicon Carbide Composite Board Material for High Density and High Reliability Packaging

(Georgia Institute of Technology, 2005-06-23) Kumbhat, Nitesh

Current board technologies are inherently performance-limited (FR-4) or cost-prohibitive (Al2O3/AlN). Next-generation high-density packaging applications would necessitate a new base substrate material to achieve ultra-fine pitch solder-joint reliability and multiple layers of fine-line wiring at low cost. The NEMI 2000 roadmap defines the need for 4-8 layers of 5-10 m wiring for future system boards. The 2003 ITRS roadmap calls for organic substrates with less than 100-m area-array pitch in the package or board by year 2010. Solder-joint reliability at such fine-pitch is a matter of concern for the industry. Use of underfills reduces thermal stresses but increases cost and, in addition, their dispensing becomes increasingly more complicated with the shorter gaps required for future interconnects. Therefore, there is a pronounced need to evaluate board materials with CTE close to that of Si for reliable flip-chip on board without underfill. Recently, a novel manufacturing process (using polymeric precursor) has been demonstrated to yield boards that have the advantages of organic boards in terms of large-area processability and machinability at potentially low-cost while retaining the high stiffness (~250 GPa) and Si-matched CTE (~2.5 ppm/㩠of ceramics. This work reports the evaluation of novel SiC-based ceramic composite board material for ultra-fine pitch solder-joint reliability without underfill and multilayer support. FE models were generated to model the behavior of flip-chips assembled without underfill and subjected to accelerated thermal cycling. These models were used to calculate solder-joint strains which have a strong direct influence on fatigue life of the solder. Multilayer structures were also simulated for thermal shock testing so as to assess via strains for microvia reliability. Via-pad misregistration was derived from the models and compared for different boards. Experiments were done to assemble flip-chips on boards without underfill followed by thermal shock testing so as to get the number of cycles to failure. To assess microvia reliability, 2 layer structures containing vias of different diameters were fabricated and subjected to thermal cycling. Via-pad misalignment was also studied experimentally. Modeling and experimental results were corroborated so as to evaluate thermomechanical suitability of C-SiC for high-density packaging requirements.