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ItemDesign and Demonstration of Mechanical and Electrical Reliability of 1-micron Redistribution Layers(Georgia Institute of Technology, 2022-12-13) Nimbalkar, PratikHigh-performance computing applications have historically driven advances in device and packaging technologies. Emergence and exponential growth of artificial intelligence, data centers and internet-of-things (IoT) have fueled the need for faster computing. The ever-growing need for faster computing has led us to the current generation integrated circuits (IC) having billions of transistors on a small area of a few square millimeters. This has brought transistor scaling to its physical and economic limits. The focus has now shifted to package-integration of chiplets due to physical and economic drawbacks associated with the System-on-chip (SoC) approach. The slow-down of Moore’s law has forced the semiconductor industry to look for alternatives to continue system scaling. Advanced semiconductor packaging is being widely accepted as the most important component for further system and performance scaling. Package integration requires high bandwidth and low latency connections between the chiplets especially between logic and memory dies. Package redistribution layers (RDL) interconnect various system components such as logic, memory and passive components. RDLs are important components of an electronic package and require significant performance improvements in the coming years to handle the requirements of higher bandwidth. This necessitates increasing the IO density and improvements in electrical performance. Increasing RDL IO density translates to scaling down RDL linewidth and spacing. Whereas, electrical performance improvement translates to minimizing electrical losses and reducing crosstalk. For reducing parasitic losses and crosstalk, lowering of RDL capacitance is critical. Traditional silicon back-end RDL uses silicon-dioxide as a dielectric which has a relatively high dielectric constant (Dk=4) and thus has fundamental limitations to improving electrical performance. Therefore, ultra-low-k (ULK) polymer dielectrics with Dk<3 are the focus of this research. Advances in photoresist materials, lithography tools and processes are necessary to enable higher RDL IO density with ULK dielectrics. In recent years, there has been significant progress in all these areas. Most of the developments have occurred in silicon interposers that continue to be the highest IO-density packaging platforms providing more than 1000 IOs/mm/layer. However, panel-scale solutions still remain at larger linewidth and spacing (L/S) >5 µm. Recent advances in panel-scale fan-out and interposer solutions have approached 2/2 µm L/S using semi-additive processing (SAP). Traditional silicon back-end RDL uses dual damascene process to form redistribution wiring. Wafer-scale processing makes the back-end RDL less cost-effective than the panel-scale SAP. Package RDL has been conventionally formed using SAP. However, there are several process limitations imposed by standard SAP in achieving sub-micron dimensions. The objectives of this research are to address the scaling limitations of multi-layer polymer RDL down to 1 µm and below. This research is focused on addressing these limitations by demonstrating designs, models, materials, and processes for - (1) high aspect ratio RDL with 1 µm L/S and 2 µm vias (2) mechanical reliability of multi-layer structure and (3) electrical reliability of ULK dielectrics.
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ItemModeling, Design and Demonstration of a Single, Innovative Metallurgical System for Socketable and Surface-Mountable Board-Level Interconnections(Georgia Institute of Technology, 2021-05-01) Gupte, Omkar DeepakOEM Microprocessors have conventionally been packaged using Land Grid Array (LGA) designs, press-fitted into sockets for ease of reworkability. However, Ball Grid Array (BGA) packages have recently become mainstream for surface mount (SMT) applications, driven by the need for miniaturization of electronic systems. While SMT processes and applications with BGA are becoming more widespread, the market need for sockets is also expected to increase significantly over the next decade. While microprocessor companies would benefit from producing a single BGA package design applicable in both socketing and SMT applications, this raises challenges for the OEM supply chain as no BGA-compatible socket is currently available. Enabling universal BGA packages compatible with both socketing and SMT processes is, therefore, critical to this industry transition. Current BGA architectures are not compatible with socketing applications as the mechanical contact between the Au paddle and the solder sphere leads to undesirable reactions, increasing the contact resistance and degrading reworkability over time. To address this challenge, surface modification of BGA spheres with multilayered thin-film metallic coatings such as Ni-Au and Bi-Au is proposed to maintain a non-reactive noble metal interface when used in a socket. This presentation provides details of the studies conducted in this research, including (1) design, diffusion modeling, and finite element modeling of such coatings with a fundamental understanding of the trade-offs between SMT and socketing applications, (2) the development, characterization and optimization of the coating on solder spheres and attach processes using an in-house developed, hybrid sputtering/electroless deposition process and conventional mass reflow with solder paste, respectively, as well as (3) reliability characterization of the modified BGA packages in socketing and SMT applications. The results establish the proposed approach as a promising technology towards the development of a reliable, universal BGA solution.
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ItemModeling, Design and Demonstration of 1 µm Wide Low Resistance Panel Redistribution Layer Technology for High Performance Computing Applications(Georgia Institute of Technology, 2020-12-06) Deprospo, BartletSince 2010, heterogeneous integration (HI) of multiple integrated circuits (ICs) on to a package substrate has become one of the most popular solutions to improve system performance and miniaturization. This HI has emerged to continue Moore’s Law scaling to support high performance computing (HPC) applications such as artificial intelligence, autonomous driving, 5G, cloud computing and wearable devices. Package substrate technology has only just begun to become a huge enabler to system scaling, beyond Moore’s Law, in terms of overall miniaturization, high bandwidth performance and high density of interconnections between heterogeneous dies to enable more operations per second. Redistribution layer (RDL) technology is the main component to interconnecting these ICs on a single package to scale beyond Moore’s Law. Examining RDL technology further it is observed that only back-end-of-line (BEOL) RDL fabricated on silicon can provide the interconnections needed for a high-performance system. However, this technology has reached a fundamental limitation due to the high resistance and capacitance of BEOL RDL that limits the further scaling of system performance. The objectives of this research are to address the scaling limitations of multi-layer polymer RDL down to 1µm and beyond. This research focuses on addressing these challenges by: (A) Electrical Design and Modeling of multi-layer polymer RDL for 4x lower resistance and 4x higher bandwidth than silicon BEOL RDL, (B) Design and demonstration of novel photoresist materials for scaling of polymer RDL well below 1µm using low-cost large panel-based tools and processes, (C) Fundamental evaluation of current substrate integration impacts on the novel photoresist material developed for scaling of polymer RDL, (D) Scaling of the semi-additive process (SAP) that is utilized in the panel-based RDL through fundamental material and process innovations.
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ItemSintered nanoporous copper die-attach interconnections: Syntheis and characterization(Georgia Institute of Technology, 2020-08-06) Mohan, KashyapTo address the demand for higher electrification and efficiency in automobiles and aviation, there is an increasing focus on developing new power electronics packaging technologies which can enable the wide-bandgap devices to operate at their full potential. In particular, new die-attach interconnection materials are needed with thermal stability at temperatures greater than 250°C, superior thermal and electrical conductivities for higher thermal dissipation and power handling. In this thesis, low-temperature, low-pressure sintering of nanoporous copper (Cu) films to form all-Cu die-attach joints is proposed as the next-generation die-attach technology capable of addressing the above-mentioned challenges. To realize the above objectives, two research tasks were identified and demonstrated. In the first task, fabrication o nanoporous Cu by chemical dealloying of amorphous Cu alloy ribbons and electroplated Cu-Zn films was explored. Fundamental relationships between the Cu-Zn electroplating parameters, composition of the electroplated films, morphology of the dealloyed films, and residual Zn after dealloying were established. Based on the results, guidelines were also framed for large-scale fabrication of nanoporous Cu films. In the second task, the effect of the sintering temperatures and sintering atmospheres on the sintering kinetics of nanoporous Cu film was explored, followed by the development of assembly parameters to enable good metallurgical bonding between nanoporous Cu and Cu metallizations. The initial assembly trials gave promising results and Cu-Cu joints with shear strengths>40MPa were achieved.
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ItemModeling, design and fabrication of substrate-embedded inductors with high inductance density and low DC resistance for integrated voltage regulators(Georgia Institute of Technology, 2020-04-28) Suresh, SrinidhiThere is an increasing need for voltage regulators to be integrated closer to active devices such as CPUs and GPUs. These integrated voltage regulators (IVRs) provide numerous performance benefits including higher efficiency, lower parasitics, and increased functionality while miniaturizing the overall system size. However, passive components i.e. inductors, generally occupy the largest volume in power distribution networks (PDNs). Therefore, realizing high-density inductors with ultra-thin form-factors is the main bottleneck to enable highly miniaturized heterogeneous integration of IVRs. An approach that can design cores and topologies with ultra-high inductance density without increasing the real-estate by using low-cost integration processes is required to address the challenges of developing inductors for IVRs. Metal-polymer composites (MPCs)-based interleaved substrate-embedded toroid inductors can meet all the criteria. MPCs as cores for inductor packages have high permeability, high resistivity, low eddy current losses and high frequency stability. An embedded interleaved toroid inductor topology using MPC cores can provide 50% more inductance, 33% higher Q-factor for the same DC resistance compared to an embedded solenoid topology. The combination of better material properties of MPCs, with an efficient toroid topology provides very high inductance densities at smaller inductor sizes, while maintaining low losses and DC resistance. The proposed work aims to improve upon current material approaches for inductor fabrication by providing better density, reduced thickness and DC resistance in a package-integrated format. This work aims to provide a basic understanding of the performance of a single-inductor using embedded toroid approach and the properties that govern its electrical behavior which can be further be scaled to coupled/tapped inductors in next-generation systems.
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ItemULTRA-LOW DIELECTRIC CONSTANT AND ULTRA-THIN POLYMER DIELECTRIC MATERIALS, PROCESSES AND RELIABILITY FOR ULTRA-HIGH BANDWIDTH COMPUTING APPLICATIONS(Georgia Institute of Technology, 2020-04-15) Dwarakanath, ShreyaThe increase in the number of connected devices in homes, cars and offices coupled with the growth of advanced data processing algorithms enabled by artificial intelligence (AI) has been driving an unprecedented need for ultra-high bandwidth computing. At the package level, the bandwidth increase can be achieved by increasing the number of input-output (I/O) connections or by increasing the data rate for each connection. The number of I/Os depends on the wiring density supported by each layer and the number of layers. These layers have to be vertically spaced at ultra-small distances to enable high-wiring density. The data rate is primarily influenced by the dielectric constant or Dk. Hence, the focus of this research is to develop ultra-low Dk and ultra-thin polymer dielectric materials, processes and reliability to meet the next-generation computing needs of ultra-high bandwidth. Silicon back-end-of line (BEOL) wiring has significant limitations such as high RC delays because of the choice of dielectric materials and cost. Current organic materials and processes are limited by their incapacity to scale to fine-features because of thick dielectric materials and poor dimensional stability of the core. This research is focused on overcoming the limitations of current approaches and demonstrating the potential for ultra-low Dk, ultra-thin polymer dielectrics to signal at higher data rates, establishing process guidelines for panel-scalable and low-cost processes and investigating the reliability of ultra-thin, ultra-low Dk dielectrics/copper interfaces, thus leading to enhanced electrical performance and lower cost compared to silicon BEOL and current organic RDL. The specific objectives of this thesis are to a) develop ultra-low-Dk (< 3.0) and ultra-thin (2-5 µm) polymer dielectric materials with optimal properties for high-signal speed, b) develop panel-scale processes for ultra-thin dielectrics with high surface planarity capable of supporting fine line/spaces of < 2 µm line width/space and < 5 µm diameter vias and, c) investigate the thermo-mechanical and chemical reliability of polymer/copper interfaces. In summary, this thesis explores polymer material classes in their compatibility for high-density RDL wiring in terms of their material properties, ease of fabricating fine-pitch features on planar and smooth surfaces and finally, in creating reliable copper/polymer interfaces with good adhesion.