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School of Materials Science and Engineering

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search.filters.applied.f.advisor: Tummala, Rao R. × End date: 2009 × Item Type: Publication × search.filters.applied.f.resourcesubtype: Dissertation ×

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Now showing 1 - 6 of 6
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    Advances in electronic packaging technologies by ultra-small microvias, super-fine interconnections and low loss polymer dielectrics
    (Georgia Institute of Technology, 2009-01-20) Sundaram, Venkatesh
    The fundamental motivation for this dissertation is to address the widening interconnect gap between integrated circuit (IC) demands and package substrates specifically for high frequency digital-RF systems applications. Moore's law for CMOS ICs predicts that transistor density on ICs will double approximately every 18 months. The current state-of-the-art in IC package substrates is at 20µm lines/spaces and 50-60µm microvia diameter using epoxy dielectrics with loss tangent above 0.01. The research targets are to overcome the barriers of current technologies and demonstrate a set of advanced materials and process technologies capable of 5-10µm lines and spaces, and 10-30µm diameter microvias in a multilayer 3-D wiring substrate using 10-25µm thin film dielectrics with loss tangent in the <0.005. The research elements are organized as follows with a clear focus on understanding and characterization of fundamental materials structure-processing-property relationships and interfaces to achieve the next generation targets. (a) Low CTE Core Substrate, (b) Low Loss Dielectrics with 25µm and smaller microvias, (c) Sub-10µm Width Cu Conductors, and (d) Integration of the various dielectric and conductor processes.
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    Fatigue modeling of nano-structured chip-to-package interconnections
    (Georgia Institute of Technology, 2009-01-09) Koh, Sau W.
    Driven by the need for increase in system¡¯s functionality and decrease in the feature size, International Technology Roadmap for Semi-conductors has predicted that integrated chip packages will have interconnections with I/O pitch of 90 nm by the year 2018. Lead-based solder materials that have been used for many decades will not be able to satisfy the thermal mechanical requirements of these fines pitch packages. Of all the known interconnect technologies, nanostructured copper interconnects are the most promising for meeting the high performance requirements of next generation devices. However, there is a need to understand their material properties, deformation mechanisms and microstructural stability. The goal of this research is to study the mechanical strength and fatigue behavior of nanocrystalline copper using atomistic simulations and to evaluate their performance as nanostructured interconnect materials. The results from the crack growth analysis indicate that nanocrystalline copper is a suitable candidate for ultra-fine pitch interconnects applications. This study has also predicts that crack growth is a relatively small portion of the total fatigue life of interconnects under LCF conditions. The simulations result conducted on the single crystal copper nano-rods show that its main deformation mechanism is the nucleation of dislocations. In the case of nanocrystalline copper, material properties such as elastic modulus and yield strength have been found to be dependent on the grain size. Furthermore, it has been shown that there is competition between the dislocation activity and grain boundary sliding as the main deformation mode This research has shown that stress induced grain coarsening is the main reason for loss of mechanical performance of nanocrystalline copper during cyclic loading. Further, the simulation results have also shown that grain growth during fatigue loading is assisted by the dislocation activity and grain boundary migration. A fatigue model for nanostructured interconnects has been developed in this research using the above observations Lastly, simulations results have shown that addition of the antimony into nanocrystalline copper will not only increase the microstructure stability, it will also increase its strength.
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    Characterization of Nanostructured Metals and Metal Nanowires for Ultra-High Density Chip-to-Package Interconnections
    (Georgia Institute of Technology, 2006-12-01) Bansal, Shubhra
    Nanocrystalline materials are being explored as potential off-chip interconnects materials for next generation microelectronics packaging. Mechanical behavior and deformation mechanisms in nanocrystalline copper and nickel have been explored. Nanostructured copper interconnections exhibit better fatigue life as compared to microcrystalline copper interconnects at a pitch of 100 and #956;m and lower. Nanocrystalline copper is quite stable upto 100 oC whereas nickel is stable even up to 400 oC. Grain boundary (GB) diffusion along with grain rotation and coalescence has been identified as the grain growth mechanism. Ultimate tensile and yield strength of nanocrystalline (nc) Cu and Ni are atleast 5 times higher than microcrystalline counterparts. Considerable amount of plastic deformation has been observed and the fracture is ductile in nature. Fracture surfaces show dimples much larger than grain size and stretching between dimples indicates localized plastic deformation. Activation energies for creep are close to GB diffusion activation energies indicating GB diffusion creep. Creep rupture at 45o to the loading axis and fracture surface shows lot of voiding and ductile kind of fracture. Grain rotation and coalescence along direction of maximum resolved shear stress plays an important role during creep. Grain refinement enhances the endurance limit and hence high cycle fatigue life. However, a deteriorating effect of grain refinement has been observed on low cycle fatigue life. This is because of the ease of crack initiation in nanomaterials. Persistent slip bands (PSBs) at an angle of 45o to loading axis are observed at higher strain ranges (> 1% for nc- Cu) with a width of about 50 nm. No relationship has been observed between PSBs and crack initiation. A non-recrystallization annealing treatment, 100 oC/ 2 hrs for nc- Cu and 250 oC/ 2 hrs for nc- Ni has been shown to improve the LCF life without lowering the strength much. Fatigue crack growth resistance is higher in nc- Cu and Ni compared to their microcrystalline counterparts. This is due to crack deflection at GBs leading to a tortuous crack path. Nanomaterials exhibit higher threshold stress intensity factors and effective threshold stress intensity is proportional to the elastic modulus of the material.
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    Chip-Package Nano-Structured Copper and Nickel Interconnections with Metallic and Polymeric Bonding Interfaces
    (Georgia Institute of Technology, 2006-11-17) Aggarwal, Ankur
    With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher interconnections densities. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches. Other approaches such as compliant interconnects require lengthy connections and are limited in terms of electrical properties. A novel chip-package interconnection technology is developed to address the IC packaging requirements and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. This thesis investigates the electrical and mechanical performance of nano-structured interconnections through modeling and test vehicle fabrication. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.
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    Ultra-thin Ceramic Films for Low-temperature Temperature Embedding of Decoupling Capacitors into Organic Printed Wiring Boards
    (Georgia Institute of Technology, 2005-10-27) Balaraman, Devarajan
    As microprocessors move towards higher frequencies, lower operating voltages and higher power consumption, supplying noise-free power to the ICs becomes increasingly challenging. Decoupling capacitors with low inductance interconnections are critical to meet the power supply impedance targets. A variety of capacitors are used today to provide decoupling at different frequencies. Surface-mount multi-layer ceramic capacitors currently used at package level provide decoupling only till about 100 MHz because of the component and lead inductances. Embedding thin film capacitors into the package can expand the operating range of package level capacitors to low GHz frequencies. Thin films with capacitance of several microfarads and organic-compatible processes are required for embedding decoupling capacitors at package level. The organic-compatible high-permittivity materials available today do not provide adequate capacitance for the application on hand. While ferroelectric thin films can provide the required capacitance, processing temperatures over 300o C are required to achieve crystalline films with high permittivity. Hence, there is a need to develop novel materials and processes to integrate decoupling capacitors into currently prevalent organic packages. To this end, hydrothermal synthesis and sol-gel synthesis of BaTiO3 films were explored in this study. BaTiO3 films were synthesized by low temperature hydrothermal conversion of metallic titanium. Hydrothermal process parameters such as bath molarity and temperature were optimized to obtain thin films with grain sizes close to 100 nm, at temperatures less than 100o C. Novel post-hydrothermal treatments were developed to improve the dielectric properties of the films. Sol-gel process requires sintering at >700o C to obtain crystalline BaTiO3 films. However, the films can be synthesized on free-standing copper foils and subsequently integrated into organic packages using lamination. Prevention of foil oxidation during sintering is critical. Nickel and titanium barriers explored in this study were ineffective due to instabilities at the interfaces. Hence, films were synthesized on bare copper foils by controlling the oxygen partial pressure during sintering. Using these techniques BaTiO3 thin films with capacitances of 400 1000 nF/cm2 and breakdown voltages of 6 15 V were demonstrated. The films synthesized via either techniques exhibited stable dielectric properties up to 8 GHz owing to fine grain sizes.
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