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School of Materials Science and Engineering

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College of Engineering

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Now showing 1 - 10 of 11

High density and high reliability thin film embedded capacitors on organic and silicon substrates

(Georgia Institute of Technology, 2008-11-20) Kumar, Manish

With the digital systems moving towards higher frequencies, lower operating voltages and higher power, supplying the required current at the right voltage and at the right time to facilitate timely switching of the CMOS circuits becomes increasingly challenging. The board level power supply cannot meet these requirements directly due to the high inductance of the package interconnections. To overcome this problem, several thin film decoupling capacitors have to be placed on the IC or close to the IC in the package. Two approaches were pursued for high-k thin film decoupling capacitors. 1) Low cost sol-gel based thin film capacitors on organic board compatible Cu-foils 2) RF-sputtered thin film capacitors on silicon substrate for silicon compatible processes While sol-gel provides cost effective technology, sputtered ferroelectric devices are more compatible from manufacturing stand point with the existing technology. Nano-crystalline barium titanate and barium strontium titanate film capacitor devices were fabricated and characterized for organic and silicon substrates respectively. Sol-gel barium titanate films were fabricated first on a bare Cu-foil and then transferred to organic board through a standard lamination process. With process optimization and film doping, a capacitance density of 3 µF/cm2 was demonstrated with breakdown voltage greater than 12V. Leakage current characteristics, breakdown voltages, and electrical reliability of the devices were significantly improved through doping of the barium titanate films and modified film chemistry. Films and interfaces were characterized with high resolution electron microscopy, SEM, XRD, and DC leakage measurements. RF sputtering was selected for ferroelectric thin film integration on silicon substrate. Barium strontium titanate (BST) films were deposited on various electrodes sputtered on silicon substrates. The main focus was to improve interface stabilities for high-k thin films on Si to yield large-area defect-free devices. Effect of bottom electrode selection and barrier layers on device yield and performance were investigated carefully. High yield and high device performance was observed for certain electrode and barrier layer combination. A capacitance density up to 1 µF/cm2 was demonstrated with a breakdown voltage above 15 V on large area, 7 mm2, devices. These two techniques can potentially meet mid-high frequency future decoupling requirements.
Thermo-mechanical reliability of ultra-thin low-loss system-on-package substrates

(Georgia Institute of Technology, 2008-11-19) Krishnan, Ganesh

Miniaturization and functionality have always governed advances in electronic system technology. To truly achieve the goal of a multi mega-functional system, advances must be made not just at the IC level, but at the system level too. This concept of tighter integration at the system level is called System-on-Package (SOP). While SOP has a wide range of applications, this work targets the mobile application space. The main driver in the mobile application space is package profile. Reduction in thickness is very critical for enabling next-generation ultra-high density mobile products. In order to pack more functionality into a smaller volume, it is absolutely imperative that package profiles are reduced. The NEMI roadmap projects that the package profile should be reduced to 200µm from the current 500µm by 2014. This work attempts to demonstrate the feasibility of ultra-thin substrates (<200µm) using a new advanced material system tailored for high-frequency mobile applications. The main barriers to adoption of thin substrates include processing challenges, concerns about via and through hole reliability and warpage. Each of these factors is studied and a full-fledged test vehicle built to demonstrate the reliability of thin substrates using the advanced low-loss RXP-4/RXP-1 material system. Finite element models are developed to provide an understanding of the factors that affect the reliability of these substrates. Finally, IC assembly is demonstrated on these substrates.
Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

(Georgia Institute of Technology, 2008-03-18) Mehrotra, Gaurav

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.
Copper to copper bonding by nano interfaces for fine pitch interconnections and thermal applications

(Georgia Institute of Technology, 2008-03-06) Jha, Gopal Chandra

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law at IC level and system miniaturization with System-On-Package (SOP) paradigm at system level, have resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. However, system miniaturization poses several electrical and thermal challenges that demand innovative solutions including advanced materials, bonding and assembly techniques. Heterogeneous material and device integration for thermal structures and IC assembly are limited by the bonding technology and the electrical and thermal impedance of the bonding interfaces. Solder - based bonding technology that is prevalent today is a major limitation to future systems. The trend towards miniaturized systems is expected to drive downscaling of IC I/O pad pitches from 40µm to 1- 5µm in future. Solder technology imposes several pitch, processability and cost restrictions at such fine pitches. Furthermore, according to International Technology Roadmap for Semiconductors (ITRS-2006), the supply current in high performance microprocessors is expected to increase to 220 A by 2012. At such supply current, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer sized technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Similarly, thermal power dissipation is growing to unprecedented high with a projected power of 198 W by 2008 (ITRS 2006). Present thermal interfaces are not adequate for such high heat dissipation. Recently, copper based thin film bonding has become a promising approach to address the abovementioned challenges. However, copper-copper direct bonding without using solders has not been studied thoroughly. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. Hence, there is a need to develop a novel low temperature copper to copper bonding process. In the present study, nanomaterials - based copper-to-copper bonding is explored and developed as an alternative to solder-based bonding. To demonstrate fine pitch bonding, the patterning of these nanoparticles is crucial. Therefore, two novel self-patterning techniques based on: 1.) Selective wetting and 2.) Selective nanoparticle deposition, are developed to address this challenge. Nanoparticle active layer facilitates diffusion and, thus, a reliable bond can be achieved using less thermal budget. Quantitative characterization of the bonding revealed good metallurgical bonding with very high bond strength. This has been confirmed by several morphological and structural characterizations. A 30-micron pitch IC assembly test vehicle is used to demonstrate fine pitch patternability and bonding. In conclusion, novel nanoparticle synthesis and patterning techniques were developed and demonstrated for low-impedance and low-cost electrical and thermal interfaces.
New Carbon-Silicon Carbide Composite Board Material for High Density and High Reliability Packaging

(Georgia Institute of Technology, 2005-06-23) Kumbhat, Nitesh

Current board technologies are inherently performance-limited (FR-4) or cost-prohibitive (Al2O3/AlN). Next-generation high-density packaging applications would necessitate a new base substrate material to achieve ultra-fine pitch solder-joint reliability and multiple layers of fine-line wiring at low cost. The NEMI 2000 roadmap defines the need for 4-8 layers of 5-10 m wiring for future system boards. The 2003 ITRS roadmap calls for organic substrates with less than 100-m area-array pitch in the package or board by year 2010. Solder-joint reliability at such fine-pitch is a matter of concern for the industry. Use of underfills reduces thermal stresses but increases cost and, in addition, their dispensing becomes increasingly more complicated with the shorter gaps required for future interconnects. Therefore, there is a pronounced need to evaluate board materials with CTE close to that of Si for reliable flip-chip on board without underfill. Recently, a novel manufacturing process (using polymeric precursor) has been demonstrated to yield boards that have the advantages of organic boards in terms of large-area processability and machinability at potentially low-cost while retaining the high stiffness (~250 GPa) and Si-matched CTE (~2.5 ppm/㩠of ceramics. This work reports the evaluation of novel SiC-based ceramic composite board material for ultra-fine pitch solder-joint reliability without underfill and multilayer support. FE models were generated to model the behavior of flip-chips assembled without underfill and subjected to accelerated thermal cycling. These models were used to calculate solder-joint strains which have a strong direct influence on fatigue life of the solder. Multilayer structures were also simulated for thermal shock testing so as to assess via strains for microvia reliability. Via-pad misregistration was derived from the models and compared for different boards. Experiments were done to assemble flip-chips on boards without underfill followed by thermal shock testing so as to get the number of cycles to failure. To assess microvia reliability, 2 layer structures containing vias of different diameters were fabricated and subjected to thermal cycling. Via-pad misalignment was also studied experimentally. Modeling and experimental results were corroborated so as to evaluate thermomechanical suitability of C-SiC for high-density packaging requirements.
Effect of intermetallic compounds on thermomechanical reliability of lead-free solder interconnects for flip-chips

(Georgia Institute of Technology, 2004-08-20) Gupta, Piyush

Georgia Techs Packaging Research Centers vision of System on Package (SOP) requires that the ball grid array (BGA) package be eliminated and the integrated circuit (IC) directly assembled on the printed wiring board (PWB). Flip-Chip on board (FCOB) emerges as a viable solution which meets the industry requirements of (i) increased I/O, (ii) increased functionality and (iii) improved performance at lower costs. Nevertheless flip-chip on board (FCOB) reliability continues to be an important concern in electronic packaging industry. Moreover transition to Pb-free solder for interconnects and continuously shrinking geometries result in new modeling challenges. In addition, the integrity of the intermetallics (IMCs) at the interfaces of the solder/PWB and solder/die is one of the determinant factors in the reliability and continuity of electrical signals in flip-chip interconnects. Pb-free solder studies for the flip-chip assembly studies are limited and simplified so far, not fully incorporating the effect of intermetallics in the reliability. New modeling challenges involve many details, from geometry to material properties. A brittle IMC will lead to a fracture at the interface. Also IMC thickness can cause the variation in stresses in the underlying layers, causing delamination. Moreover IMC morphology can also depend on the metal finishes on the PWB. In this work, a combined numerical and experimental program has been developed to address the challenges mentioned above. The flip-chip on board assembly is modeled in 3-D for reliability studies, taking into consideration material non linearities and a 104 order of geometric variation to capture the die size in mm to sub-micron intermetallic thickness. The study intends to determine the stresses induced at the critical interfaces under thermo-mechanical loading incorporating the intermetallic material properties. Various failure modes of these assemblies were studied. Experiments were carried out for comparative reliability studies of Pb-free solder with eutectic Pb-based solder. Intermetallic formation and growth are characterized during thermal aging and its effect on reliability is determined. Parameters affecting intermetallic like under-bump Metallurgy (UBM) thicknesses are varied and its effect evaluated. Moreover experiments with three new substrate pad finishes on PWB are carried out to evaluate them as an alternative to Electroless nickel immersion gold (ENIG) for new Pb-free solder. The final aim of this study is to reach a better understanding of the reliability issues in FCOB.
Thermomechanical characterization of materials formicrominiaturized system board requirements

(Georgia Institute of Technology, 2003-08) Bansal, Shubhra
Warpage characterization and lithographic limitations of FR-4 for SOP global interconnect needs

(Georgia Institute of Technology, 2002-08) Banerji, Sounak
Processing and characterization of polymer-ceramic composite thin film dielectrics for embedded decoupling applications

(Georgia Institute of Technology, 2001-12) Mani, Rajesh
Development and integration of thin film zinc oxide integral resistors in SOP

(Georgia Institute of Technology, 2001-05) Morales, Hector Roberto