Organizational Unit:
School of Materials Science and Engineering

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Now showing 1 - 2 of 2
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    Characterization of Nanostructured Metals and Metal Nanowires for Ultra-High Density Chip-to-Package Interconnections
    (Georgia Institute of Technology, 2006-12-01) Bansal, Shubhra
    Nanocrystalline materials are being explored as potential off-chip interconnects materials for next generation microelectronics packaging. Mechanical behavior and deformation mechanisms in nanocrystalline copper and nickel have been explored. Nanostructured copper interconnections exhibit better fatigue life as compared to microcrystalline copper interconnects at a pitch of 100 and #956;m and lower. Nanocrystalline copper is quite stable upto 100 oC whereas nickel is stable even up to 400 oC. Grain boundary (GB) diffusion along with grain rotation and coalescence has been identified as the grain growth mechanism. Ultimate tensile and yield strength of nanocrystalline (nc) Cu and Ni are atleast 5 times higher than microcrystalline counterparts. Considerable amount of plastic deformation has been observed and the fracture is ductile in nature. Fracture surfaces show dimples much larger than grain size and stretching between dimples indicates localized plastic deformation. Activation energies for creep are close to GB diffusion activation energies indicating GB diffusion creep. Creep rupture at 45o to the loading axis and fracture surface shows lot of voiding and ductile kind of fracture. Grain rotation and coalescence along direction of maximum resolved shear stress plays an important role during creep. Grain refinement enhances the endurance limit and hence high cycle fatigue life. However, a deteriorating effect of grain refinement has been observed on low cycle fatigue life. This is because of the ease of crack initiation in nanomaterials. Persistent slip bands (PSBs) at an angle of 45o to loading axis are observed at higher strain ranges (> 1% for nc- Cu) with a width of about 50 nm. No relationship has been observed between PSBs and crack initiation. A non-recrystallization annealing treatment, 100 oC/ 2 hrs for nc- Cu and 250 oC/ 2 hrs for nc- Ni has been shown to improve the LCF life without lowering the strength much. Fatigue crack growth resistance is higher in nc- Cu and Ni compared to their microcrystalline counterparts. This is due to crack deflection at GBs leading to a tortuous crack path. Nanomaterials exhibit higher threshold stress intensity factors and effective threshold stress intensity is proportional to the elastic modulus of the material.
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    Chip-Package Nano-Structured Copper and Nickel Interconnections with Metallic and Polymeric Bonding Interfaces
    (Georgia Institute of Technology, 2006-11-17) Aggarwal, Ankur
    With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher interconnections densities. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches. Other approaches such as compliant interconnects require lengthy connections and are limited in terms of electrical properties. A novel chip-package interconnection technology is developed to address the IC packaging requirements and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. This thesis investigates the electrical and mechanical performance of nano-structured interconnections through modeling and test vehicle fabrication. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.