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School of Materials Science and Engineering

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search.filters.applied.f.advisor: Tummala, Rao R. × End date: 2006 × Start date: 2003 × Item Type: Publication × search.filters.applied.f.isOrgUnitOfPublicationTitle: College of Engineering ×

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Now showing 1 - 6 of 6
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    Characterization of Nanostructured Metals and Metal Nanowires for Ultra-High Density Chip-to-Package Interconnections
    (Georgia Institute of Technology, 2006-12-01) Bansal, Shubhra
    Nanocrystalline materials are being explored as potential off-chip interconnects materials for next generation microelectronics packaging. Mechanical behavior and deformation mechanisms in nanocrystalline copper and nickel have been explored. Nanostructured copper interconnections exhibit better fatigue life as compared to microcrystalline copper interconnects at a pitch of 100 and #956;m and lower. Nanocrystalline copper is quite stable upto 100 oC whereas nickel is stable even up to 400 oC. Grain boundary (GB) diffusion along with grain rotation and coalescence has been identified as the grain growth mechanism. Ultimate tensile and yield strength of nanocrystalline (nc) Cu and Ni are atleast 5 times higher than microcrystalline counterparts. Considerable amount of plastic deformation has been observed and the fracture is ductile in nature. Fracture surfaces show dimples much larger than grain size and stretching between dimples indicates localized plastic deformation. Activation energies for creep are close to GB diffusion activation energies indicating GB diffusion creep. Creep rupture at 45o to the loading axis and fracture surface shows lot of voiding and ductile kind of fracture. Grain rotation and coalescence along direction of maximum resolved shear stress plays an important role during creep. Grain refinement enhances the endurance limit and hence high cycle fatigue life. However, a deteriorating effect of grain refinement has been observed on low cycle fatigue life. This is because of the ease of crack initiation in nanomaterials. Persistent slip bands (PSBs) at an angle of 45o to loading axis are observed at higher strain ranges (> 1% for nc- Cu) with a width of about 50 nm. No relationship has been observed between PSBs and crack initiation. A non-recrystallization annealing treatment, 100 oC/ 2 hrs for nc- Cu and 250 oC/ 2 hrs for nc- Ni has been shown to improve the LCF life without lowering the strength much. Fatigue crack growth resistance is higher in nc- Cu and Ni compared to their microcrystalline counterparts. This is due to crack deflection at GBs leading to a tortuous crack path. Nanomaterials exhibit higher threshold stress intensity factors and effective threshold stress intensity is proportional to the elastic modulus of the material.
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    Chip-Package Nano-Structured Copper and Nickel Interconnections with Metallic and Polymeric Bonding Interfaces
    (Georgia Institute of Technology, 2006-11-17) Aggarwal, Ankur
    With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher interconnections densities. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches. Other approaches such as compliant interconnects require lengthy connections and are limited in terms of electrical properties. A novel chip-package interconnection technology is developed to address the IC packaging requirements and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. This thesis investigates the electrical and mechanical performance of nano-structured interconnections through modeling and test vehicle fabrication. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.
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    Ultra-thin Ceramic Films for Low-temperature Temperature Embedding of Decoupling Capacitors into Organic Printed Wiring Boards
    (Georgia Institute of Technology, 2005-10-27) Balaraman, Devarajan
    As microprocessors move towards higher frequencies, lower operating voltages and higher power consumption, supplying noise-free power to the ICs becomes increasingly challenging. Decoupling capacitors with low inductance interconnections are critical to meet the power supply impedance targets. A variety of capacitors are used today to provide decoupling at different frequencies. Surface-mount multi-layer ceramic capacitors currently used at package level provide decoupling only till about 100 MHz because of the component and lead inductances. Embedding thin film capacitors into the package can expand the operating range of package level capacitors to low GHz frequencies. Thin films with capacitance of several microfarads and organic-compatible processes are required for embedding decoupling capacitors at package level. The organic-compatible high-permittivity materials available today do not provide adequate capacitance for the application on hand. While ferroelectric thin films can provide the required capacitance, processing temperatures over 300o C are required to achieve crystalline films with high permittivity. Hence, there is a need to develop novel materials and processes to integrate decoupling capacitors into currently prevalent organic packages. To this end, hydrothermal synthesis and sol-gel synthesis of BaTiO3 films were explored in this study. BaTiO3 films were synthesized by low temperature hydrothermal conversion of metallic titanium. Hydrothermal process parameters such as bath molarity and temperature were optimized to obtain thin films with grain sizes close to 100 nm, at temperatures less than 100o C. Novel post-hydrothermal treatments were developed to improve the dielectric properties of the films. Sol-gel process requires sintering at >700o C to obtain crystalline BaTiO3 films. However, the films can be synthesized on free-standing copper foils and subsequently integrated into organic packages using lamination. Prevention of foil oxidation during sintering is critical. Nickel and titanium barriers explored in this study were ineffective due to instabilities at the interfaces. Hence, films were synthesized on bare copper foils by controlling the oxygen partial pressure during sintering. Using these techniques BaTiO3 thin films with capacitances of 400 1000 nF/cm2 and breakdown voltages of 6 15 V were demonstrated. The films synthesized via either techniques exhibited stable dielectric properties up to 8 GHz owing to fine grain sizes.
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    New Carbon-Silicon Carbide Composite Board Material for High Density and High Reliability Packaging
    (Georgia Institute of Technology, 2005-06-23) Kumbhat, Nitesh
    Current board technologies are inherently performance-limited (FR-4) or cost-prohibitive (Al2O3/AlN). Next-generation high-density packaging applications would necessitate a new base substrate material to achieve ultra-fine pitch solder-joint reliability and multiple layers of fine-line wiring at low cost. The NEMI 2000 roadmap defines the need for 4-8 layers of 5-10 m wiring for future system boards. The 2003 ITRS roadmap calls for organic substrates with less than 100-m area-array pitch in the package or board by year 2010. Solder-joint reliability at such fine-pitch is a matter of concern for the industry. Use of underfills reduces thermal stresses but increases cost and, in addition, their dispensing becomes increasingly more complicated with the shorter gaps required for future interconnects. Therefore, there is a pronounced need to evaluate board materials with CTE close to that of Si for reliable flip-chip on board without underfill. Recently, a novel manufacturing process (using polymeric precursor) has been demonstrated to yield boards that have the advantages of organic boards in terms of large-area processability and machinability at potentially low-cost while retaining the high stiffness (~250 GPa) and Si-matched CTE (~2.5 ppm/㩠of ceramics. This work reports the evaluation of novel SiC-based ceramic composite board material for ultra-fine pitch solder-joint reliability without underfill and multilayer support. FE models were generated to model the behavior of flip-chips assembled without underfill and subjected to accelerated thermal cycling. These models were used to calculate solder-joint strains which have a strong direct influence on fatigue life of the solder. Multilayer structures were also simulated for thermal shock testing so as to assess via strains for microvia reliability. Via-pad misregistration was derived from the models and compared for different boards. Experiments were done to assemble flip-chips on boards without underfill followed by thermal shock testing so as to get the number of cycles to failure. To assess microvia reliability, 2 layer structures containing vias of different diameters were fabricated and subjected to thermal cycling. Via-pad misalignment was also studied experimentally. Modeling and experimental results were corroborated so as to evaluate thermomechanical suitability of C-SiC for high-density packaging requirements.
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    Effect of intermetallic compounds on thermomechanical reliability of lead-free solder interconnects for flip-chips
    (Georgia Institute of Technology, 2004-08-20) Gupta, Piyush
    Georgia Techs Packaging Research Centers vision of System on Package (SOP) requires that the ball grid array (BGA) package be eliminated and the integrated circuit (IC) directly assembled on the printed wiring board (PWB). Flip-Chip on board (FCOB) emerges as a viable solution which meets the industry requirements of (i) increased I/O, (ii) increased functionality and (iii) improved performance at lower costs. Nevertheless flip-chip on board (FCOB) reliability continues to be an important concern in electronic packaging industry. Moreover transition to Pb-free solder for interconnects and continuously shrinking geometries result in new modeling challenges. In addition, the integrity of the intermetallics (IMCs) at the interfaces of the solder/PWB and solder/die is one of the determinant factors in the reliability and continuity of electrical signals in flip-chip interconnects. Pb-free solder studies for the flip-chip assembly studies are limited and simplified so far, not fully incorporating the effect of intermetallics in the reliability. New modeling challenges involve many details, from geometry to material properties. A brittle IMC will lead to a fracture at the interface. Also IMC thickness can cause the variation in stresses in the underlying layers, causing delamination. Moreover IMC morphology can also depend on the metal finishes on the PWB. In this work, a combined numerical and experimental program has been developed to address the challenges mentioned above. The flip-chip on board assembly is modeled in 3-D for reliability studies, taking into consideration material non linearities and a 104 order of geometric variation to capture the die size in mm to sub-micron intermetallic thickness. The study intends to determine the stresses induced at the critical interfaces under thermo-mechanical loading incorporating the intermetallic material properties. Various failure modes of these assemblies were studied. Experiments were carried out for comparative reliability studies of Pb-free solder with eutectic Pb-based solder. Intermetallic formation and growth are characterized during thermal aging and its effect on reliability is determined. Parameters affecting intermetallic like under-bump Metallurgy (UBM) thicknesses are varied and its effect evaluated. Moreover experiments with three new substrate pad finishes on PWB are carried out to evaluate them as an alternative to Electroless nickel immersion gold (ENIG) for new Pb-free solder. The final aim of this study is to reach a better understanding of the reliability issues in FCOB.
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