(Georgia Institute of Technology, 2020-08-06)
Mohan, Kashyap
To address the demand for higher electrification and efficiency in automobiles and aviation, there is an increasing focus on developing new power electronics packaging technologies which can enable the wide-bandgap devices to operate at their full potential. In particular, new die-attach interconnection materials are needed with thermal stability at temperatures greater than 250°C, superior thermal and electrical conductivities for higher thermal dissipation and power handling. In this thesis, low-temperature, low-pressure sintering of nanoporous copper (Cu) films to form all-Cu die-attach joints is proposed as the next-generation die-attach technology capable of addressing the above-mentioned challenges. To realize the above objectives, two research tasks were identified and demonstrated. In the first task, fabrication o nanoporous Cu by chemical dealloying of amorphous Cu alloy ribbons and electroplated Cu-Zn films was explored. Fundamental relationships between the Cu-Zn electroplating parameters, composition of the electroplated films, morphology of the dealloyed films, and residual Zn after dealloying were established. Based on the results, guidelines were also framed for large-scale fabrication of nanoporous Cu films. In the second task, the effect of the sintering temperatures and sintering atmospheres on the sintering kinetics of nanoporous Cu film was explored, followed by the development of assembly parameters to enable good metallurgical bonding between nanoporous Cu and Cu metallizations. The initial assembly trials gave promising results and Cu-Cu joints with shear strengths>40MPa were achieved.
(Georgia Institute of Technology, 2018-07-27)
Shahane, Ninad Makarand
The objectives of this work are to design and demonstrate novel chip-to-package substrate Cu-based interconnections without solders at 20µm pitch for power handling at current densities exceeding 10E5 A/cm2, high-throughput manufacturability, and thermomechanical reliability without cracking low-K on-chip dielectrics. To realize these objectives, two approaches are proposed, based on design of nanoscale bonding interfaces for assembly throughput, and electrical, thermal and reliability performances. The first approach utilizes novel Au-based bimetallic thin-films applied on Cu bumps and pads to prevent oxidation and enhance bonding reactivity. This approach focuses on thin-film interdiffusion in nanocrystalline Cu-Ni/Pd-Au layers and the reaction kinetics behind intermetallic compound (IMC) formation at the bonded interfaces. A high-speed thermocompression assembly process is developed and validated to boost throughput. Furthermore, the stability of these interconnection systems is demonstrated through extensive thermomechanical and electro migration reliability testing. The second approach introduces low-modulus nanocopper foam caps on bulk Cu micro-bumps to act as compliant and reactive bonding interfaces. A fundamental understanding of this sintering process is proposed and contrasted to that of conventional nanoparticle-based systems. Using co-electrodeposition techniques, patterned nano-Cu foam capped interconnections are fabricated and a first assembly of such compliant interconnections is demonstrated. In conclusion, these unique Cu interconnection technologies address cost, manufacturability, and scalability and therefore, have the potential to become the next interconnection nodes for high-performance systems.