Title:
Architectural Mechanisms for Explicit Communication in Shared Memory Multiprocessors
Architectural Mechanisms for Explicit Communication in Shared Memory Multiprocessors
Author(s)
Ramachandran, Umakishore
Shah, Gautam H.
Sivasubramaniam, Anand
Singla, Aman
Yanasak, Ivan
Shah, Gautam H.
Sivasubramaniam, Anand
Singla, Aman
Yanasak, Ivan
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Abstract
The goal of this work is to explore architectural mechanisms for supporting
explicit communication in cache-coherent shared memory multiprocessors. The
motivation stems from the observation that applications display wide diversity
in terms of sharing characteristics and hence impose different communication
requirements on the system. Explicit communication mechanisms would allow
tailoring the coherence management under software control to match these
differing needs and strive to provide a close approximation to a zero overhead
machine from the application perspective. Toward achieving these goals, we
first analyze the characteristics of sharing observed in certain specific
applications. We then use these characteristics to synthesize explicit
communication primitives. The proposed primitives allow selectively updating
a set of processors, or requesting a stream of data ahead of its intended use.
These primitives are essentially generalizations of prefetch and poststore,
with the ability to specify the sharer set for poststore either statically or
dynamically. The proposed primitives are to be used in conjunction with an
underlying invalidation based protocol. Used in this manner, the resulting
memory system can dynamically adapt itself to performing either invalidations
or updates to match the communication needs. Through application driven
performance study we show the utility of these mechanisms in being able to
reduce and tolerate communication latencies.
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Date Issued
1994
Extent
215151 bytes
Resource Type
Text
Resource Subtype
Technical Report