Title:
Timepatch: A Novel Technique for the Parallel Simulation of Multiprocessor Caches
Timepatch: A Novel Technique for the Parallel Simulation of Multiprocessor Caches
Authors
Shah, Gautam H.
Ramachandran, Umakishore
Fujimoto, Richard M.
Ramachandran, Umakishore
Fujimoto, Richard M.
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Abstract
We present a new technique for the parallel simulation of cache
coherent shared memory multiprocessors. Our technique is based
on the fact that the functional correctness of the simulation
can be decoupled from its timing correctness. Thus in our
simulations we can exploit as much parallelism as is available
in the application without being constrained by conservative
scheduling mechanisms that might limit the available parallelism
in order to guarantee the timing correctness of the simulation.
Further, application specific details (which can be gleaned from
the compiler) such as data layout in the caches of the target
architecture can be exploited to reduce the overhead of the
simulation. The simulation correctness is guaranteed by patching
the performance related timing information at specific points
in the program (commensurate with the programming model). There
are two principal advantages to this technique: being able to
simulate larger parallel systems (both problem size and number
of processors) than is feasible to simulate sequentially; and
being able to speed up the simulation compared to a sequential
simulator. For proof of concept, we have implemented this
technique for an execution-driven parallel simulator on the
KSR-2, a cache-coherent shared memory machine, for a target
architecture that uses an invalidation-based protocol. We
validate the performance statistics gathered from this
simulator (using traces) by comparing it against a sequential
simulator. We show that the method is both viable and promises
to offer significant speedups with the number of processors.
We provide a detailed performance study of our technique using
some benchmark application programs.
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Date Issued
1994
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337147 bytes
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Text
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Technical Report