An Exploration of Potential Pathways Toward Emerging Electronic Devices with Ferroelectric Materials

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Hsu, Chia-Sheng
Naeemi, Azad
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In the relentless pursuit of Moore's law, device scaling down to the nanometer regime has gradually reached a bottleneck as the power dissipation in microchips becomes a more and more challenging concern. Therefore, emerging technologies beyond CMOS are in urgent need of development. Among many proposed emerging devices, we primarily focus our research attention on the negative capacitance phenomenon in ferroelectrics and the magnetoelectric effect in multiferroics for low power device applications in this thesis. To assess the potential application of the negative capacitance effect, we first implement a physics-based circuit-compatible model of single domain ferroelectric materials for the study of the performance of negative capacitance field-effect transistors at the device and circuit levels. The single domain ferroelectric model is further extended to a multi-domain model by adopting the phase field formalism to capture the polycrystalline nature of ferroelectric films. For realistic logic device applications, however, the physical mechanisms behind the experimental observation of hysteresis-free negative capacitance behaviors have not yet been clear. Therefore, we dedicate our research efforts to the study of such a key phenomenon for the realization of ultra-low power negative capacitance field effect transistors. In addition, with proper free energy contributions included to describe the experimentally observed two-step polarization switching process in bismuth ferrite, a unified micromagnetic/ferroelectric simulation framework is developed to model the deterministic switching dynamics and thermal stability of the single-domain BFO/CoFe heterojunction. Lastly, a comprehensive thesis overview and the important topics for future works are given, especially the trapped charge dynamics in ferroelectric field effect transistors, which is the major reliability concern for the memory device realization.
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