Title:
HIGH THROUGHPUT OPENCL ACCELERATOR FOR SPARSE ALGEBRA
HIGH THROUGHPUT OPENCL ACCELERATOR FOR SPARSE ALGEBRA
Author(s)
Ramchandani, Dheeraj
Advisor(s)
Kim, Hyesoon
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Abstract
With the emergence of FPGA boards equipped with High Bandwidth Memory (HBM2), these boards have become more attractive for implementing memory-intensive applications. High-Level Synthesis (HLS) compilers also have eased programming of FPGAs, allowing developers to program FPGAs in high-level languages such as C, C++, and OpenCL, leading to a faster development cycle. Even though the programming of FPGAs has become easier, it is not easy to obtain maximum performance for a memory-intensive application without careful hardware consideration and optimizing techniques (temporal parallelism, spatial parallelism, memory alignment, etc.). In this thesis, we implement a tree-based architecture to efficiently compute SpMV operations on the Alveo U280 Xilinx board. We also discuss and evaluate various HLS optimizing techniques, quantitatively( throughput), which are necessary to achieve high performance.
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Date Issued
2021-12-14
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Text
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Thesis