Title:
Low-Voltage Soft-Switching Solid-State Transformer (S4T) Enabled by the Synchronous Reverse Blocking Switch
Low-Voltage Soft-Switching Solid-State Transformer (S4T) Enabled by the Synchronous Reverse Blocking Switch
Author(s)
Marellapudi, Aniruddh
Advisor(s)
Divan, Deepakraj M.
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Abstract
The objective of this research is to demonstrate a high-efficiency, low-voltage Soft-Switching Solid-State Transformer (S4T) enabled by the Synchronous Reverse Blocking (RB) Switch, a patent-pending method to seamlessly integrate dual-active-switch structures into the S4T topology to minimize conduction losses in low-voltage, high-current applications. The S4T is a universal converter with the ability to interface single-phase, three-phase, and DC sources, and features bidirectional power transfer, buck-boost functionality, high-frequency isolation, low electromagnetic interference (EMI) through controlled dv/dt, and zero-voltage switching (ZVS) operation for all main devices over the entire load range to minimize switching losses. Significant success has been achieved in applying the S4T to industrial voltages (600 VAC and 1000 VDC) and medium voltage AC and DC (MVDC and MVAC) through the use of 3.3 kV silicon-carbide (SiC) devices and series-stacking of S4T modules. However, applying the topology to interface with low-voltage, high-current sources and loads has been challenging due to the high conduction losses associated with conventional reverse blocking switch structures composed of one active switching device, such as an IGBT or a MOSFET, in series with a diode, usually a SiC Schottky diode. Replacing the conventional RB switch structure with a dual-active-switch configuration, specifically one composed of two low on-resistance N-channel MOSFETs, presents an opportunity to significantly reduce semiconductor conduction losses and increase converter efficiency. However, as the PN-junction MOSFET body diode replaces the series SiC Schottky diode of conventional RB structures, body diode reverse recovery must be mitigated to prevent large device voltage stresses, increased device losses, additional EMI, and reduced converter reliability. This thesis presents the device-level and system-level validation of the Synchronous Reverse Blocking Switch within the S4T, showcasing the ability of the method to significantly reduce conduction losses while also evidencing benign reverse recovery behavior, unlocking several high-efficiency low-voltage applications of the S4T topology.
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Date Issued
2020-12-04
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Thesis