Modeling, design, materials, processes and reliability of multi-layer redistribution wiring layers on glass substrates for next generation of high-performance computing applications

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Nair, Chandrasekharan
Tummala, Rao R.
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There is a growing demand for high performance computing with miniaturization in many electronic systems such as servers for cloud computing, accurate weather prediction, smart mobile and wearable devices and autonomous driving cars. The development of 2.5D silicon interposers in 2010 for heterogeneous integration of graphical processing unit (GPU) to high bandwidth memory (HBM) dies addressed this demand to a certain extent. The back-end-of-line (BEOL) RDL processes in silicon interposers have reached the peak with data rate per signal trace due to the high resistance and capacitance of BEOL RDL, limiting the system bandwidth for 2.5D silicon interposers. The cost of such interposers is also high for large body size substrates (> 1200 sq. mm) due to the fabrication on wafer-based platforms and hence, such interposers have been primarily been used today for cost-insensitive applications like cloud computing. To address these limitations, panel-based organic package substrates with a vast range of body sizes (500-5000 sq.mm) have been under development. These low-cost, high performance panel-based substrates will bring down the cost of high-performance computing systems as well as introduce 2.5D interposers for consumer applications like mobile computing. However, such panel-based substrates have not been able to scale multi-layer polymer RDL below 5 µm RDL which is the primary requirement for 2.5D interposer substrates. The objectives of this research are to address the scaling limitations of multi-layer polymer RDL down to 2 µm and below. This research is focused on addressing these limitations by: (A) Modeling for layer-to-layer registration to predict the fundamental limit of capture pad required for laminate and glass core substrates (B) Design of multi-layer polymer RDL for 5X bandwidth and 3X lower latency than silicon BEOL RDL (C) Design and demonstration of novel materials and processes for scaling polymer RDL well below 2 µm using low-cost panel-based tools and processes (D) Reliability analysis of 2 µm multi-layer polymer RDL and identifying future needs for novel polymer dielectrics for scaling polymer RDL to sub 1-micron features.
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