Modeling, design and demonstration of through-package-vias in panel-based polycrystalline silicon interposers for high performance, high reliability and low cost

Chen, Qiao

Title:

Modeling, design and demonstration of through-package-vias in panel-based polycrystalline silicon interposers for high performance, high reliability and low cost

dc.contributor.advisor	Tummala, Rao R.
dc.contributor.author	Chen, Qiao
dc.contributor.committeeMember	Rohatgi, Ajeet
dc.contributor.committeeMember	Lim, Sung Kyu
dc.contributor.committeeMember	Sitaraman, Suresh
dc.contributor.committeeMember	Sundaram, Venky
dc.contributor.department	Electrical and Computer Engineering
dc.date.accessioned	2015-06-08T18:35:48Z
dc.date.available	2015-06-08T18:35:48Z
dc.date.created	2015-05
dc.date.issued	2015-04-02
dc.date.submitted	May 2015
dc.date.updated	2015-06-08T18:35:48Z
dc.description.abstract	Silicon interposers with TSVs (through-silicon-vias) have been developed in single-crystalline silicon wafer to achieve the high I/O (Input/Output) density. However, single-crystalline silicon interposers suffer a few problems such as cost, electrical performance and reliability. To overcome these shortcomings, an entirely different approach using polycrystalline silicon interposers with thick polymer liners are proposed by Georgia Tech Packaging Research Center, aiming to achieve lower cost silicon interposers with high performance and reliability. The objective of this research is to explore and demonstrate thin polycrystalline silicon as a suitable interposer material to achieve high performance and high reliability TPVs (through-package-vias) in polycrystalline silicon materials with lower cost. Three fundamental challenges were defined, including: 1) low resistivity of the polycrystalline silicon, resulting in high electrical loss; 2) reliability problems resulting from CTE (coefficient of thermal expansion) mismatch between silicon and Cu, and 3) handling and processing of thin silicon panels. A three-dimensional EM (electromagnetic) model was developed to simulate insertion loss and crosstalk of TPVs and compared with TSVs. It has been shown thick polymer liner is effective in addressing the fundamental challenge of low resistivity for the polycrystalline silicon material, leading to better electrical performance of TPVs than TSVs. Parametric studies indicate that thicker sidewall liners result in better electrical performance. A two-dimensional axisymmetric model was established to simulate the first principal stresses in silicon and shear stresses in TPV under thermal cycling. TPVs with thick polymer liners present both smaller principal stresses and shear stresses than TSVs due to the low modulus of polymer. Parametric studies suggest that sidewall liners act as stress buffers and thicker liners result in better mechanical performance. Design guidelines based on simulation results were used in TPV demonstration and test vehicle fabrication. Fracture strength of polycrystalline silicon panel has been fundamentally studied with four-point bending tool and Weibull plot. Surface polymer liners on both sides were introduced to improve the handling of thin silicon panels. Quantitative study showed higher characteristic fracture strength for the panel with surface liners than raw silicon panel. Low cost and double-side processes have been developed for TPV fabrication including UV (ultraviolet) lasers for TPV formation, double laser method for liner fabrication and electroless Cu for seed formation. Key steps and mechanisms for aforementioned processes were summarized and discussed. Polycrystalline silicon interposers with TPVs and up to four metal RDLs (re-distribution layers) were designed, fabricated and characterized. Measurement results showed low insertion loss for both TPVs and CPW (co-planar waveguide) transmission lines. Good model to hardware correlation was also observed. Reliability test vehicles of polycrystalline silicon interposers were also designed and fabricated for thermal cycling test. TPVs survived 4000 cycles without significant resistance changes. SEM imaging on the cross-section of the samples confirmed no Cu or silicon cracking. Magnified images around corner also suggested good adhesion at Cu/liner and silicon/liner interfaces.
dc.description.degree	Ph.D.
dc.format.mimetype	application/pdf
dc.identifier.uri	http://hdl.handle.net/1853/53568
dc.language.iso	en_US
dc.publisher	Georgia Institute of Technology
dc.subject	Silicon interposer package
dc.subject	Polycrystalline silicon panel
dc.subject	Through-package-vias
dc.title	Modeling, design and demonstration of through-package-vias in panel-based polycrystalline silicon interposers for high performance, high reliability and low cost
dc.type	Text
dc.type.genre	Dissertation
dspace.entity.type	Publication
local.contributor.advisor	Tummala, Rao R.
local.contributor.corporatename	School of Electrical and Computer Engineering
local.contributor.corporatename	College of Engineering
relation.isAdvisorOfPublication	fe05ddb2-e957-4584-ac88-58a197df62aa
relation.isOrgUnitOfPublication	5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication	7c022d60-21d5-497c-b552-95e489a06569
thesis.degree.level	Doctoral