Title:
An Analysis of Register Allocation Techniques in the Context Of A RISC-V Processor
An Analysis of Register Allocation Techniques in the Context Of A RISC-V Processor
Author(s)
Viszlai, Joshua
Advisor(s)
Sarkar, Vivek
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Abstract
This research looks at the register allocation phase of a compiler for programs running on a RISC-V machine. Register allocation algorithms were applied to a test program compiled through an LLVM-based toolchain to be run on a RISC-V simulator. Four register allocation algorithms were used in compilation of the libquantum test case from the SPECint2006 CPU test suite. The number of loads and stores when executed on a RISC-V simulator were observed, and the results showed that a large determinant of performance was the extent of saving and restoring registers during function calls.
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Date Issued
2020-05
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Text
Resource Subtype
Undergraduate Thesis