Title:
Designing heterogeneous many-core processors to provide high performance under limited chip power budget

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dc.contributor.advisor Lee, Hsien-Hsin Sean
dc.contributor.author Woo, Dong Hyuk en_US
dc.contributor.committeeMember Lim, Sung Kyu
dc.contributor.committeeMember Prvulovic, Milos
dc.contributor.committeeMember Wolf, Marilyn
dc.contributor.committeeMember Yalamanchili, Sudhakar
dc.contributor.department Electrical and Computer Engineering en_US
dc.date.accessioned 2011-03-04T21:05:34Z
dc.date.available 2011-03-04T21:05:34Z
dc.date.issued 2010-10-04 en_US
dc.description.abstract This thesis describes the efficient design of a future many-core processor that can provide higher performance under the limited chip power budget. To achieve such a goal, this thesis first develops an analytical framework within which computer architects can estimate achievable performance improvement of different many-core architectures given the same power budget. From this study, this thesis found that a future many-core processor needs (1) energy-efficient parallel cores and (2) a high-performance sequential core. Based on these observations, this thesis proposes an energy-efficient broad-purpose acceleration layer that can be snapped on top of a conventional general-purpose processor. In addition to such an energy-efficient parallel cores, this thesis also proposes different architectural techniques to further boost the performance of sequential computation while those parallel cores are idle. In particular, this thesis develops low-cost architectural techniques to enhance the memory performance of a host core by utilizing those idle parallel cores. This idea is evaluated in two different system architectures: one with the aforementioned acceleration layer and the other with an emerging integrated CPU and GPU chip. en_US
dc.description.degree Ph.D. en_US
dc.identifier.uri http://hdl.handle.net/1853/37294
dc.publisher Georgia Institute of Technology en_US
dc.subject Heterogeneous many-core architecture en_US
dc.subject.lcsh Heterogeneous computing
dc.subject.lcsh Parallel processing (Electronic computers)
dc.subject.lcsh Multiprocessors
dc.subject.lcsh Microprocessors
dc.subject.lcsh High performance processors
dc.title Designing heterogeneous many-core processors to provide high performance under limited chip power budget en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
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