Ferroelectric and Monolithic 3D (M3D) Memory Technologies for High-Performance, Energy-Efficient Computing
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Aabrar, Khandker Akif
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Abstract
Present-day hardware with limited on-chip memory capacity falls short of meeting the speed and energy-efficiency requirement for data-intensive applications such as Artificial Intelligence due to the need for expensive data transfer between processor and off-chip memory. The objective of this research is to mitigate the energy-inefficiency and latency by developing ultra-high density cache memory and computational memory for enabling near-memory computing and in-memory computing. First, a back-end-of-line (BEOL)-compatible dual-gate (DG) W-doped In2O3 (IWO) field-effect transistor (FET) with high-performance, low-leakage and improved reliability is demonstrated, which is promising as access/read transistors for realizing M3D embedded-DRAM. The proposed DG IWO FET synergistically improves the device performance and VT stability, thereby breaking the performance-stability trade-off typically observed in BEOL FETs. Furthermore, a comprehensive reliability model is developed to elucidate the VT shift mechanisms. Second, we study and develop ferroelectric (FE) FET based computational memory for accelerating in-situ training and edge inference in deep neural networks (DNNs). On that front, we develop a scaled Si-channel FE-FinFET process and explores its potential application as a 2bit/cell weight cell for feature extraction and DNN inference. Lastly, this thesis proposes a novel idea of engineering ferroelectric gate stack using superlattice (SL) structure which enhances multi-state programmability of FEFET and thus can enable denser memory and novel functionality such as analog weight cell to accelerate in-situ training and inference of DNN. We experimentally demonstrate a BEOL SL FEFET analog weight cell with a record-high 1000 analog conductance states exhibiting a high degree of linearity and symmetry. We also demonstrate 8 non-overlapping programmed states for the SL FEFET which enables enhanced multi-level-cell operation (3bit/cell) over conventional FEFETs.
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2024-09-06
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Dissertation (PhD)