Title:
Targeting multi-core clock performance gains: vertically integrated adaptation and prototyping

dc.contributor.author Chatterjee, Abhijit
dc.contributor.corporatename Georgia Institute of Technology. Office of Sponsored Programs en_US
dc.contributor.corporatename Georgia Institute of Technology. School of Electrical and Computer Engineering en_US
dc.date.accessioned 2019-07-03T18:57:37Z
dc.date.available 2019-07-03T18:57:37Z
dc.date.issued 2012-06
dc.description Issued as final report en_US
dc.description.abstract A low cost post-manufacturing testing and speed tuning methodology is proposed in a multi-processor system. The goal of this research is to develop a methodology that allows the “safe” speed of each core in a large CMP to be determined under the assumption that some speed defects and design bugs are likely to escape conventional delay testing procedures. en_US
dc.description.sponsorship National Science Foundation (U.S.) en_US
dc.identifier.uri http://hdl.handle.net/1853/61488
dc.language.iso en_US en_US
dc.publisher Georgia Institute of Technology en_US
dc.relation.ispartofseries School of Electrical and Computer Engineering ; Project no. 110093 en_US
dc.subject Multi-core systems en_US
dc.subject Multiprocessors en_US
dc.title Targeting multi-core clock performance gains: vertically integrated adaptation and prototyping en_US
dc.type Text
dc.type.genre Technical Report
dspace.entity.type Publication
local.contributor.author Chatterjee, Abhijit
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
local.contributor.corporatename Office of Sponsored Programs
local.relation.ispartofseries OSP Final Research Reports
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