A Unified Model of Pattern-Matching Circuit Architectures

Clark, Christopher R.; Schimmel, D. E. (David E.)

Title:

A Unified Model of Pattern-Matching Circuit Architectures

dc.contributor.author	Clark, Christopher R.
dc.contributor.author	Schimmel, D. E. (David E.)
dc.date.accessioned	2006-02-07T20:07:11Z
dc.date.available	2006-02-07T20:07:11Z
dc.date.issued	2005
dc.description.abstract	There has been a significant volume of recent work on FPGA designs for pattern matching. Although various pattern-matching architectures have been presented, attempts to compare different designs have been inconclusive, or even misleading, due to the lack of a common evaluation framework. In this paper, we present an analytical model of FPGA pattern-matching architectures that quanti-tatively expresses the relationships between pattern properties, circuit area, and circuit delay. We derive equations that show how the performance of each architecture is dependent on the properties of the pattern set. This model enables many different pattern-matching architectures to be compared in order to determine the optimal design for a given pattern-matching application.	en
dc.format.extent	298168 bytes
dc.format.mimetype	application/pdf
dc.identifier.uri	http://hdl.handle.net/1853/7712
dc.language.iso	en_US	en
dc.publisher	Georgia Institute of Technology	en
dc.relation.ispartofseries	CERCS;GIT-CERCS-05-20	en
dc.subject	FPGA designs for pattern matching
dc.subject	Common evaluation framework
dc.subject	Analytical models
dc.subject	Pattern matching
dc.subject	FPGA
dc.subject	Field programmable gate arrays
dc.title	A Unified Model of Pattern-Matching Circuit Architectures	en
dc.type	Text
dc.type.genre	Technical Report
dspace.entity.type	Publication
local.contributor.corporatename	Center for Experimental Research in Computer Systems
local.relation.ispartofseries	CERCS Technical Report Series
relation.isOrgUnitOfPublication	1dd858c0-be27-47fd-873d-208407cf0794
relation.isSeriesOfPublication	bc21f6b3-4b86-4b92-8b66-d65d59e12c54