Methodologies for Modeling and Optimization of 2.5-D and 3-D Integration Architectures for Compute-In-Memory Applications
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Kaul, Ankit
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Abstract
The objective of this research is to investigate power delivery network (PDN) and thermal management constraints in emerging 3-D heterogeneous integration (HI) architectures for compute-in-memory (CIM) applications. First, design trade-offs in the PDN of bridge-chip based 2.5-D heterogeneous platforms are investigated. It is demonstrated that including a PDN in the bridge-chip can provide significant reduction in DC-IR drop, Ldi/dt noise, and high-frequency ripple compared to the baseline. Second, a comprehensive design-space exploration of PDN design for 3-D-HI CIM hardware is presented. A methodology is proposed to evaluate and quantify trade-offs between power delivery design parameters and CIM performance metrics. Subsequently, a device-integration methodology is proposed to quantify the thermal-driven impact of integration architectures on resistive random-access memory (RRAM) reliability for CIM applications. Two 3-D-HI accelerator designs are benchmarked against monolithic 2-D and balanced integration design parameters are reported. Finally, a back-end-of-line (BEOL)-embedded chiplet integration architecture (polylithic 3-D) is proposed. Polylithic 3-D integration represents a densely integrated system divided into multiple device tiers where custom chiplets can be embedded into the back end of a primary tier with extremely efficient signaling and large bandwidth density. Design optimization strategies for PDN and thermal management in polylithic 3-D integration are presented and benchmarked against conventional 3-D integration. The potential impact of this research and potential future directions are summarized.
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Date
2023-08-28
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Dissertation