Broadband Phase Locked Loop for Multi-Band Millimeter-Wave 5G Communication
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Abstract
According to one embodiment, a phase locked loop (PLL) circuit includes a first voltage controlled oscillator (VCO) to generate a first signal having a first frequency and a second VCO to generate a second signal having a second frequency. The PLL circuit includes a multiplexer coupled to the first VCO, the second VCO, and a feedback loop. The PLL circuit includes a control logic to select either the first VCO or the second VCO using the multiplexer to feed back a signal using the feedback loop, and a phase frequency detector coupled to the first VCO, the second VCO, and the feedback loop, where the phase frequency detector is configured to receive a reference signal and the feedback signal to tracking a frequency and a phase of the first or the second generated signal using the reference signal and the feedback signal.
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10/15/2019