Comparative Analysis of Memory Hierarchies for Novel Paradigms in Superconducting Logic Families
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Wen, Shunzhi
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This thesis aims to propose a memory system solution to alleviate the constraints of superconducting logic families on architectural design. Due to the limitations on circuit density and fanout, multi-ported caches are not feasible in the realm of superconducting electronics. As an alternative, the project focuses on a banked cache system allowing independent access to memory partitions per bank, enabling parallel memory accesses. With advanced cache bank selection policies, like PRIM, we can achieve load balance across cache banks with strong robustness against various access patterns. Other designs such as LSQ and MSHR are employed to further improve the efficiency of memory accesses. Additionally, a comprehensive examination of memory technologies is conducted to fulfill the needs of each level in the memory hierarchy. The primary goal of this work is to illuminate the challenges faced by the memory system for superconducting logic architectures and shed light on a viable approach to solve it.
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Undergraduate Research Option Thesis