Title:
Void Formation Study of Flip Chip in Package Using No-Flow Underfill

dc.contributor.author Lee, Sangil en_US
dc.contributor.author Yim, Myung Jin en_US
dc.contributor.author Master, Raj N. en_US
dc.contributor.author Wong, C. P. en_US
dc.contributor.author Baldwin, Daniel F. en_US
dc.contributor.corporatename Georgia Institute of Technology. School of Mechanical Engineering en_US
dc.contributor.corporatename Georgia Institute of Technology. School of Materials Science and Engineering en_US
dc.contributor.corporatename Advanced Micro Devices (Firm) en_US
dc.date.accessioned 2009-04-28T19:47:02Z
dc.date.available 2009-04-28T19:47:02Z
dc.date.issued 2008-10
dc.description ©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. en_US
dc.description DOI: 10.1109/TEPM.2008.2002951 en_US
dc.description.abstract The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between solder bumps or inside the solder bumps during the no-flow underfill assembly process of FCIP devices have been typically considered one of the critical concerns affecting assembly yield and reliability performance. In this paper, the plausible causes of underfill void formation in FCIP using no-flow underfill were investigated through systematic experimentation with different types of test vehicles. For instance, the effects of process conditions, material properties, and chemical reaction between the solder bumps and no-flow underfill materials on the void formation behaviors were investigated in advanced FCIP assemblies. In this investigation, the chemical reaction between solder and underfill during the solder wetting and underfill cure process has been found to be one of the most significant factors for void formation in high I/O and fine-pitch FCIP assembly using no-flow underfill materials. en_US
dc.identifier.citation IEEE Transactions on Electronics Packaging Manufacturing, Vol. 31, no. 4, October 2008, 297-305 en_US
dc.identifier.issn 1521-334X
dc.identifier.uri http://hdl.handle.net/1853/27851
dc.language.iso en_US en_US
dc.publisher Georgia Institute of Technology en_US
dc.publisher.original Institute of Electrical and Electronics Engineers, Inc. en_US
dc.subject Chemical reaction en_US
dc.subject Flip chip en_US
dc.subject Fine pitch en_US
dc.subject High I/O en_US
dc.subject Density en_US
dc.subject No-flow underfill en_US
dc.subject Reliability en_US
dc.subject Void formation en_US
dc.title Void Formation Study of Flip Chip in Package Using No-Flow Underfill en_US
dc.type Text
dc.type.genre Article
dspace.entity.type Publication
local.contributor.author Wong, C. P.
local.contributor.corporatename School of Materials Science and Engineering
local.contributor.corporatename College of Engineering
relation.isAuthorOfPublication 76540daf-1e96-4626-9ec1-bc8ed1f88e0a
relation.isOrgUnitOfPublication 21b5a45b-0b8a-4b69-a36b-6556f8426a35
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
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