Understanding the Dynamic Operation Limits and Reliability of Highly-Scaled Silicon Germanium Heterojunction Bipolar Transistors
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Lee, Harrison P.
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Abstract
The objective of this work is to expand upon understood reliability effects in silicon- germanium (SiGe) heterojunction bipolar transistors (HBTs) and bridge the gap between a device-level understanding of reliability and system-level performance of circuits using HBTs. The aim is to better understand the safe limits of transistor biasing and investigate dynamic, transient swings past the traditional DC-defined safe operating area (SOA) of the transistor.
Chapter 1 describes the need for understanding the reliability physics of SiGe HBTs. This chapter will describe how the device SOA is measured and defined and will briefly discuss the physical mechanisms at the limit of transistor operation, including avalanche multiplication, thermal runaway, and base current reversal. This chapter will also briefly discuss the design of an additional, medium breakdown (MB) transistor profile which al- lows for a designer to include aggressively scaled high speed HBTs with a higher break- down transistor in the same technology platform.
Chapter 2 discusses the common damage mechanisms at play in SiGe HBTs, namely mixed-mode (MM) and high-current (HC). These two damage mechanisms occur at the outer limits of the device SOA, and understanding of these mechanisms is critical to under- stand how to maximize the potential of SiGe HBTs by operating at the edge of the device limits. Understanding damage mechanisms will also enable designers to consider the in- tended lifetime of the circuit to ensure the system meets specifications across the entire target lifetime.
Chapter 3 uses pulsed-voltage measurements to investigate the dynamic breakdown of SiGe HBTs under high field. As a high voltage is applied to the collector of the device, self-heating within the transistor activates a positive feedback mechanism between device temperature, collector current, and power consumed, resulting in an uncontrollable thermal runaway. Measurements are performed by using pulsed voltage in conjunction with an emitter ballast resistor to reduce the effect of self-heating on the transistor. Results show that as self-heating is reduced, the maximum voltage limit of the device increases, and breakdown switches from being thermally dominated to impact-ionization dominated. This is significant because high-speed RF and mmWave signals switch at faster speeds than the device self-heating, and thus at high frequency, the dominant breakdown mechanism may be different from the conventional DC-defined SOA.
Chapter 4 compares the performance and reliability tradeoffs of cascode amplifier cells designed using different transistor profiles. Test structures were created using the medium breakdown (MB) and high performance (HP) variants of an advanced SiGe HBT technology (GlobalFoundries 9HP). Small-signal (fT /fmax) and large-signal (gain compression) measurements are performed to quantify the performance difference between cascodes with HP and MB devices in the common base (CB) stage, and DC+RF stress measurements are used to identify the reliability difference. The results show that large cascode cells oper- ating well below the transistor peak fT show roughly equivalent performance between HP and MB, and that the cascode reliability is largely dependent upon the selected bias point and load-line swing in conjunction with the top device selection. Thus, it may be possible for circuit designers to optimize the reliability of a circuit without sacrificing performance by carefully selecting the device profile and the dynamic output swing of the cascode cell.
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