TCAD Modelling and PDK Development For 3nm GAAFET Technology
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Kini, Akshata Ashok
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Abstract
This thesis aims to contribute to a comprehensive exploration of 3nm Gate All-Around Field-Effect Transistors (GAAFET) technology through the integration of transistor modelling of GAAFET, Standard Cell layout design, library characterization, Back-End Of Line (BEOL) optimisation, and validation by running a full physical design flow. In addition, a novel TCAD model for GAAFET transistor is developed using Sentaurus Process including Buried Power Rail (BPR) technology to facilitate the in-depth study and simulation of 3nm GAAFETs. With the current model designed adhering to foundry requirements, variability studies of different electrical and physical parameters are performed as a part of the thesis.
Going beyond transistor modelling, our collaborative efforts involve the creation of layouts for standard cells using Custom Compiler, coupled with execution of Layout v/s Schematic (LVS) and Design Rule Checking (DRC) checks. Circuits with simple gates like AND, and OR are designed and simulated, and standard cell libraries are characterised for timing, power, and area. To benchmark the characterised standard cell libraries, Synthesis and Place and Route (PnR) are to be done on an industrial test case. Furthermore, an existing design of BEOL is used and simulated using Coventor to study impacts on Power Performance Area (PPA) in 3nm technology incorporating various interconnect materials.
This holistic approach aims to provide a comprehensive framework for 3nm Process Design Kit (PDK) development. Since this collaborative effort incorporates an exhaustive
cycle from transistor modelling to running a PnR on a test case, design considerations at each step of the cycle can be analysed and optimized to provide valuable insights aimed at
improving different areas such as circuit performance, reliability, power, and area.
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2024-05-06
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