Title:
SoftCache Architecture

dc.contributor.advisor Lee, Hsien-Hsin Sean
dc.contributor.advisor Ramachandran, Umakishore
dc.contributor.author Fryman, Joshua Bruce en_US
dc.contributor.committeeMember Mackenzie, Kenneth
dc.contributor.committeeMember Pande, Santosh
dc.contributor.committeeMember Schimmel, David
dc.contributor.committeeMember Schwan, Karsten
dc.contributor.department Computing en_US
dc.date.accessioned 2005-09-16T15:11:20Z
dc.date.available 2005-09-16T15:11:20Z
dc.date.issued 2005-07-19 en_US
dc.description.abstract Multiple trends in computer architecture are beginning to collide as process technology reaches ever smaller feature sizes. Problems with managing power, access times across a die, and increasing complexity to sustain growth are now blocking commercial products like the Pentium 4. These problems also occur in the embedded system space, albeit in a slightly different form. However, as process technology marches on, today's high-performance space is becoming tomorrow's embedded space. New techniques are needed to overcome these problems. In this thesis, we propose a novel architecture called SoftCache to address these emerging issues for embedded systems. We reduce the on-die memory controller infrastructure which reduces both power and space requirements, using the ubiquitous network device arena as a proving ground of viability. In addition, the SoftCache achieves further power and area savings by converting on-die cache structures into directly addressable SRAM and reducing or eliminating the external DRAM. To avoid the burden of programming complexity this approach presents to the application developer, we provide a transparent client-server dynamic binary translation system that runs arbitrary ELF executables on a stripped-down embedded target. One drawback to such a scheme lies in the overhead of additional instructions required to effect cache behavior, particularly with respect to data caching. Another drawback is the power use when fetching from remote memory over the network. The SoftCache comprises a dynamic client-server translation system on simplified hardware, targeted at Intel XScale client devices controlled from servers over the network. Reliance upon a network server as a ``backing store' introduces new levels of complexity, yet also allows for more efficient use of local space. The explicitly software managed aspects create a cache of variable line size, full associativity, and high flexibility. This thesis explores these particular issues, while approaching everything from the perspective of feasibility and actual architectural changes. en_US
dc.description.degree Ph.D. en_US
dc.format.extent 13412077 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/7205
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.subject Low-power en_US
dc.subject Computer architecture
dc.subject Embedded systems
dc.subject Cache design
dc.subject Sensor networks
dc.title SoftCache Architecture en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.advisor Ramachandran, Umakishore
local.contributor.corporatename College of Computing
relation.isAdvisorOfPublication ecee44ae-00f0-4d06-b7f7-0967613ef340
relation.isOrgUnitOfPublication c8892b3c-8db6-4b7b-a33a-1b67f7db2021
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