MODELING AND BENCHMARKING OF SPINTRONIC DEVICES AND THEIR APPLICATIONS
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Liao, Yu-Ching
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Abstract
Spintronic devices are promising candidates for low power applications such as logic and memory due to the characteristics of non-volatility, scalability, and fast switching speed. To evaluate the array-level performances of various spintronic memory devices, we have benchmarked spin-transfer torque magnetorestrictive random-access memory (STT-MRAM), spin-orbit torque MRAM (SOT-MRAM), voltage-controlled exchange coupling MRAM (VCEC-MRAM), and magnetoelectric MRAM (ME-MRAM). Among them, electric-field driven devices such as magnetoelectric (ME) device and the VCEC-MRAM can eliminate the joule heating energy thus is potentially more energy efficient than the current-controlled devices.
Bismuth ferrite (BiFeO3) is a multiferroic material with the properties of ferroelectricity, antiferromagnetism, and weak ferromagnetism at room temperature. By combining BiFeO3 with a ferromagnet such as CoFe to form a BiFeO3/CoFe heterojunction, one can manipulate the magnetic state of CoFe by applying an external electric field. However, the switching mechanisms of the ferroelectric and the magnetic order of the BiFeO3 and CoFe are less understood which limits the estimation of the delay time and the write energy of the ME device. To evaluate the potential performance of this voltage-controlled BFO/CoFe heterojunction device in memory or logic application, we present a unified micromagnetic/ferroelectric simulation framework that can model the transient response and the switching behaviors of both BFO and CoFe layers. In addition, the important material parameters such as the interface exchange coupling coefficient are extracted from the experiments. Next, we build a physics-based compact model of the BFO/CoFe heterojunction to simulate the ME device in the circuit level. The results from our compact model closely match very well with those from the micromagnetic models when simulating the magnetization dynamics of BFO and CoFe. Using the compact model we developed, the SPICE simulation shows that ME-MRAM can potentially operate with a lower write energy compared to the STT-MRAM, SOT-MRAM or even SRAM when the coercive voltage of the BFO layer is as small as 20mV. Last, we model and benchmark the read and write performances of SOT-MRAM using various SOT materials including heavy metals, alloys, Weyl semi-metals, and topological insulators. The non-ideal factors such as current-shunting effect, current crowding effect, and the variability are included. Our results indicate that spintronic memory devices are prospective candidates in the embedded memory application due to the better energy efficiency and smaller layout area compared to SRAM.
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Date
2021-07-28
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Dissertation