Title:
Virtual qualification methodology for next-generation area-array packages

dc.contributor.advisor Sitaraman, Suresh K.
dc.contributor.author Raghunathan, Rajiv en_US
dc.contributor.department Mechanical engineering en_US
dc.date.accessioned 2007-12-20T12:30:48Z
dc.date.available 2007-12-20T12:30:48Z
dc.date.issued 2000-08 en_US
dc.description.degree M.S. en_US
dc.identifier.bibid 562921 en_US
dc.identifier.uri http://hdl.handle.net/1853/18849
dc.publisher Georgia Institute of Technology en_US
dc.rights Access restricted to authorized Georgia Tech users only. en_US
dc.subject.lcsh Packaging en_US
dc.subject.lcsh Packaging Testing en_US
dc.subject.lcsh Electronic circuits Design and construction en_US
dc.title Virtual qualification methodology for next-generation area-array packages en_US
dc.type Text
dc.type.genre Thesis
dspace.entity.type Publication
local.contributor.advisor Sitaraman, Suresh K.
local.contributor.corporatename George W. Woodruff School of Mechanical Engineering
local.contributor.corporatename College of Engineering
relation.isAdvisorOfPublication 86701d63-9ca5-4060-89f8-aca6e0b267f6
relation.isOrgUnitOfPublication c01ff908-c25f-439b-bf10-a074ed886bb7
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
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