Hardware-Algorithm Co-Design for Energy-Efficient and Low-Latency Domain-Specific Machine Learning Systems
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Sharma, Sudarshan
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Abstract
This dissertation develops hardware–software co-design methodologies across multiple stages of the machine-learning (ML) system stack, spanning sensor-to-model interfaces, neural network architectures, and hardware accelerators. Modern ML workloads must balance competing demands of latency, energy, throughput, and accuracy, creating a multidimensional design space where no single configuration suffices. By jointly optimizing algorithms and hardware, this research demonstrates how tailored co-design strategies can deliver substantial performance and efficiency gains.
At the sensor-ML interface, we introduce mixed-signal compute-in-memory accelerators for efficient feature extraction and employ Quantization-Aware Training (QAT) with low-Hamming-weight binary representations, significantly reducing inference energy costs. At the neural network level, we design ChirpNet, a radar-specific architecture that sequentially processes Frequency Modulated Continuous Wave (FMCW) chirps, thereby lowering memory and compute requirements. We also propose LUGA, an adaptive ML-sensor feedback framework that dynamically tunes sensing resolution and model complexity based on real-time confidence estimates, improving energy efficiency. At the accelerator level, we develop hardware-algorithm co-design techniques for distributed SAT solving using stochastic recurrent neural networks (S-RNNs). Leveraging low-precision weights and tensor-parallel execution with Reduce-Scatter communication, we achieve notable speedups and reduced latency.
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2025-08-22
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Dissertation (PhD)