Title:
Energy efficient and SCA-resistant cryptographic hardware for IOT applications
Energy efficient and SCA-resistant cryptographic hardware for IOT applications
| dc.contributor.advisor | Mukhopadhyay, Saibal | |
| dc.contributor.author | Singh, Arvind | |
| dc.contributor.committeeMember | Krishna, Tushar | |
| dc.contributor.committeeMember | Beyah, Raheem | |
| dc.contributor.committeeMember | Kim, Hyesoon | |
| dc.contributor.committeeMember | De, Vivek | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.date.accessioned | 2019-08-21T13:54:58Z | |
| dc.date.available | 2019-08-21T13:54:58Z | |
| dc.date.created | 2019-08 | |
| dc.date.issued | 2019-07-23 | |
| dc.date.submitted | August 2019 | |
| dc.date.updated | 2019-08-21T13:54:58Z | |
| dc.description.abstract | Security and privacy of critical and sensitive data is a major challenge for all computing systems, however, network-connected IoT devices have been overlooked with respect to device-related security risks owing to lack of resources at IoT edge nodes. Moreover, encryption algorithms implemented in hardware emit information about the key through physical side channels leading to research challenges in designing energy-efficient, compact and side channel attack (SCA) resistant cryptographic hardware for IoT applications. This thesis investigates alternative hardware architectures for SIMON for higher energy-efficiency and design of lightweight SCA countermeasures utilizing on-chip integrated power-management and clocking techniques. We propose round unrolled datapath for SIMON implemented in ASIC and FPGA platforms to simultaneously improve energy-efficiency and SCA resistance. The optimized SIMON engine is applied to a low-power image sensor node to analyze the overheads incurred to enable security at IoT-edge nodes. We further propose lightweight countermeasures utilizing on-chip integrated fully inductive voltage regulator (FIVR) and digital low-dropout (DLDO) regulator along-with all-digital clock modulation (ADCM) circuit to improve SCA resistance of SIMON and advanced encryption standard (AES) encryption engines. The proposed FIVR, DLDO designs with 128-bit SIMON and AES cores and randomization circuits are prototyped in two testchips in 130nm CMOS process and SCA measurements demonstrate improved resistance with respect to test vector leakage assessment (TVLA) and correlation power and EM analysis (CPA & CEMA) attacks. | |
| dc.description.degree | Ph.D. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/61785 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | Side channel attacks | |
| dc.subject | Power management | |
| dc.subject | Digital LDO | |
| dc.subject | Clock modulation | |
| dc.subject | Noise Injection | |
| dc.subject | DPA | |
| dc.subject | SNR | |
| dc.subject | CPA | |
| dc.subject | CEMA | |
| dc.subject | TVLA | |
| dc.subject | AES | |
| dc.subject | SIMON | |
| dc.subject | Encryption | |
| dc.subject | IoT | |
| dc.subject | Security | |
| dc.title | Energy efficient and SCA-resistant cryptographic hardware for IOT applications | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Mukhopadhyay, Saibal | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | 62df0580-589a-4599-98af-88783123945a | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
| thesis.degree.level | Doctoral |