Title:
MOS transistor and interconnection path strength simulation algorithm and hardware acceleration on a two-dimensional processing element array
MOS transistor and interconnection path strength simulation algorithm and hardware acceleration on a two-dimensional processing element array
| dc.contributor.advisor | Schlag, Jay H. | |
| dc.contributor.author | Owen, Henry L., III | en_US |
| dc.contributor.department | Electric Engineering | en_US |
| dc.date.accessioned | 2007-03-01T18:52:05Z | |
| dc.date.available | 2007-03-01T18:52:05Z | |
| dc.date.issued | 1989-08 | en_US |
| dc.description.degree | Ph.D. | |
| dc.format.extent | 237 bytes | |
| dc.format.mimetype | text/html | |
| dc.identifier.bibid | 326912 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1853/13549 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | en_US |
| dc.rights | Access restricted to authorized Georgia Tech users only. | en_US |
| dc.subject.lcsh | Computer-aided design | en_US |
| dc.subject.lcsh | Engineering mathematics | en_US |
| dc.title | MOS transistor and interconnection path strength simulation algorithm and hardware acceleration on a two-dimensional processing element array | en_US |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.author | Owen, Henry L., III | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAuthorOfPublication | d3983de1-d725-47f4-b653-a318b39d8fd9 | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 |
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