A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC).

dc.contributor.advisor Meindl, James D.
dc.contributor.advisor Wills, D. Scott
dc.contributor.author Nugent, Steven Paul en_US
dc.contributor.committeeMember Davis, Jeffrey A.
dc.contributor.committeeMember Swaminathan, Madhavan
dc.contributor.committeeMember Paul A. Kohl
dc.contributor.committeeMember William R. Callen
dc.contributor.department Electrical and Computer Engineering en_US
dc.date.accessioned 2005-07-28T17:56:51Z
dc.date.available 2005-07-28T17:56:51Z
dc.date.issued 2005-04-14 en_US
dc.description.abstract Future opportunities for gigascale integration will be governed by a hierarchy of theoretical and practical limits that can be codified as follows: fundamental, material, device, circuit, and system. An exponential increase in on-chip integration is driving System-on-Chip (SoC) methodologies as a dominant design solution for gigascale ICs. Therefore, a second generation generic systems simulator (GENESYS) is developed to address a need for rapid assessment of technology/architecture tradeoffs for multi-billion transistor SoCs while maintaining the depth of core modeling codified in the hierarchy of limits. A newly developed system methodology incorporates a hiearchical block-based model, a dual interconnect distribution for both local and global interconnects, a generic on-chip bus model, and cell placement algorithms. A comparison of simulation results for five commercial SoC implementations shows increased accuracy in predicting die size, clock frequency, and total power dissipation. ITRS projections for future technology requirments are applied with results indicating that increasing static power dissipation is a key impediment to making continued improvements in chip performance. Additionally, simulations of a generic chip multi-processor architecture utilizing several interconnect schemes shows that the most promising candidate for the future of on-chip global interconnect networks will be hierarchical bus structures providing a high degree of connectivity while maintaining high operating frequencies. en_US
dc.description.degree Ph.D. en_US
dc.format.extent 1039916 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/6885
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.subject Chip modeling en_US
dc.subject Performance modeling
dc.subject Simulator
dc.subject Gigascale
dc.subject Chip modeling
dc.subject GENESYS
dc.subject.lcsh Integrated circuits Very large scale integration Design and construction Computer simulation en_US
dc.subject.lcsh System design Computer simulation en_US
dc.title A Second Generation Generic Systems Simulator (GENESYS) for a Gigascale System-on-a-Chip (SoC). en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
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