Title:
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB-Refinements
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB-Refinements
| dc.contributor.author | Manolios, Panagiotis | |
| dc.contributor.author | Srinivasan, Sudarshan Kumar | |
| dc.date.accessioned | 2005-03-29T21:24:42Z | |
| dc.date.available | 2005-03-29T21:24:42Z | |
| dc.date.issued | 2003 | |
| dc.description.abstract | We show how to automatically verify that a complex XScale-like pipelined machine model is a WEB-refinement of an instruction set architecture model, which implies that the machines satisfy the same safety and liveness properties. Automation is achieved by reducing the WEB-refinement proof obligation to a formula in the logic of Counter arithmetic with Lambda expressions and Uninterpreted functions (CLU). We use UCLID to transform the resulting CLU formula into a CNF formula, which is then checked with a SAT solver. We define several XScale-like models with out of order completion, including models with precise exceptions, branch prediction, and interrupts. We use two types of refinement maps. In one, flushing is used to map pipelined machine states to instruction set architecture states; in the other, we use the commitment approach, which is the dual of flushing, since partially completed instructions are invalidated. We present experimental results for all the machines mode! led, including verification times. For our application, we found that the SAT solver Siege provides superior performance over Chaff and that the amount of time spent proving liveness when using the commitment approach is less than 1% of the overall verification time, whereas when flushing is employed, the liveness proof accounts for about 10% of the verification time. | en |
| dc.format.extent | 68581 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/5953 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | en |
| dc.relation.ispartofseries | CERCS;GIT-CERCS-03-17 | |
| dc.subject | Boolean satisfiability problem | en |
| dc.subject | Commitment approach | en |
| dc.subject | Liveness | en |
| dc.subject | SAT | en |
| dc.subject | SAT solvers | en |
| dc.subject | Siege | en |
| dc.subject | Verification time | en |
| dc.subject | WEB-refinement proof obligation | |
| dc.subject | XScale-like models | |
| dc.title | Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB-Refinements | en |
| dc.type | Text | |
| dc.type.genre | Technical Report | |
| dspace.entity.type | Publication | |
| local.contributor.corporatename | Center for Experimental Research in Computer Systems | |
| local.relation.ispartofseries | CERCS Technical Report Series | |
| relation.isOrgUnitOfPublication | 1dd858c0-be27-47fd-873d-208407cf0794 | |
| relation.isSeriesOfPublication | bc21f6b3-4b86-4b92-8b66-d65d59e12c54 |