Title:
High performance, low-power and robust multi-gigabit wire-line design
High performance, low-power and robust multi-gigabit wire-line design
Author(s)
Mukherjee, Tonmoy Shankar
Advisor(s)
Kornegay, Kevin T.
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Abstract
The object of this research is to develop robust wire-line systems which demonstrate high performance while simultaneously consuming low power. The main focus of this work is the Clock and Data Recovery (CDR) system, which is the primary circuit of any modern wire-line transceiver. Different techniques starting from circuit-level to system-level have been investigated in this work to improve the performance of multi-gigabit CDRs. A 62 GHz bandwidth amplifier has been presented to address the need for a scalable amplifier for CDR needs. A new technique has been proposed to improve the radiation immunity of latches, to reduce the BER in CDRs occurring due to package radiations. An injection-lock based clock recovery method was investigated as an alternative to PLL based CDRs as they can be used for burst-mode wire-line communication. The investigation yielded the vulnerability of the method to jitter (false-locking and high jitter transfer), the attenuation of which is critical to commercial CDRs. A novel false-lock detector system has been proposed and demonstrated for the first time as a robust solution to the issue of false-locking of CDRs due to repetitive patterns. The implementation of the final CDR system required the use of an L-C tank VCO, the components of which are generic for all commercial CDRs. A new systematic layout technique for the VCO has been proposed and demonstrated in this work to substantially improve the layout area and the associated parasitics, approximately by 70 %. This new layout addresses a critical yet often neglected part of VCO design. Furthermore, a new concept has been proposed to optimize static dividers with respect to their power consumption and number of devices.
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Date Issued
2010-03-15
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Text
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Dissertation