Title:
CMOS RF SOC Transmitter Front-End, Power Management and Digital Analog Interface
CMOS RF SOC Transmitter Front-End, Power Management and Digital Analog Interface
| dc.contributor.advisor | Laskar, Joy | |
| dc.contributor.author | Leung, Matthew Chung-Hin | en_US |
| dc.contributor.committeeMember | John D Cressler | |
| dc.contributor.committeeMember | Kevin T Kornegay | |
| dc.contributor.department | Electrical and Computer Engineering | en_US |
| dc.date.accessioned | 2008-09-17T19:28:27Z | |
| dc.date.available | 2008-09-17T19:28:27Z | |
| dc.date.issued | 2008-05-19 | en_US |
| dc.description.abstract | With the growing trend of wireless electronics, frequency spectrum is crowded with different applications. High data transfer rate solutions that operate in license-exempt frequency spectrum range are sought. The most promising candidate is the 60 GHz multi-giga bit transfer rate millimeter wave circuit. In order to provide a cost-effective solution, circuits designed in CMOS are implemented in a single SOC. In this work, a modeling technique created in Cadence shows an error of less than 3dB in magnitude and 5 degree in phase for a single transistor. Additionally, less than 3dB error of power performance for the PA is also verified. At the same time, layout strategies required for millimeter wave front-end circuits are investigated. All of these combined techniques help the design converge to one simulation platform for system level simulation. Another aspect enabling the design as a single SOC lies in integration. In order to integrate digital and analog circuits together, necessary peripheral circuits must be designed. An on-chip voltage regulator, which steps down the analog power supply voltage and is compatible with digital circuits, has been designed and has demonstrated an efficiency of 65 percent with the specific area constraint. The overall output voltage ripple generated is about 2 percent. With the necessary power supply voltage, gate voltage bias circuit designs have been illustrated. They provide feasible solutions in terms of area and power consumption. Temperature and power supply sensitivities are minimized in first two designs. Process variation is further compensated in the third design. The third design demonstrates a powerful solution that each aspect of variations is well within 10%. As the DC conditions are achieved on-chip for both the digital and analog circuits, digital and analog circuits must be connected together with a DAC. A high speed DAC is designed with special layout techniques. It is verified that the DAC can operate at a speed higher than 3 Gbps from the pulse-shaping FIR filter measurement result. With all of these integrated elements and modeling techniques, a high data transfer rate CMOS RF SOC operating at 60 GHz is possible. | en_US |
| dc.description.degree | M.S. | en_US |
| dc.identifier.uri | http://hdl.handle.net/1853/24664 | |
| dc.publisher | Georgia Institute of Technology | en_US |
| dc.subject | R2R | en_US |
| dc.subject | Hysteretic | en_US |
| dc.subject | EHF | en_US |
| dc.subject | Power amplifier | en_US |
| dc.subject | Digital-to-analog converter | en_US |
| dc.subject.lcsh | Network performance (Telecommunication) | |
| dc.subject.lcsh | Data transmission systems | |
| dc.subject.lcsh | Millimeter wave devices | |
| dc.title | CMOS RF SOC Transmitter Front-End, Power Management and Digital Analog Interface | en_US |
| dc.type | Text | |
| dc.type.genre | Thesis | |
| dspace.entity.type | Publication | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 |
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