Title:
Aniruddh Ramrakhyani Thesis
Aniruddh Ramrakhyani Thesis
| dc.contributor.advisor | Krishna, Tushar | |
| dc.contributor.author | Ramrakhyani, Aniruddh | |
| dc.contributor.committeeMember | Gavrilovska, Ada | |
| dc.contributor.committeeMember | Yalamanchili, Sudhakar | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.date.accessioned | 2017-06-07T17:49:24Z | |
| dc.date.available | 2017-06-07T17:49:24Z | |
| dc.date.created | 2017-05 | |
| dc.date.issued | 2017-04-26 | |
| dc.date.submitted | May 2017 | |
| dc.date.updated | 2017-06-07T17:49:24Z | |
| dc.description.abstract | The demise of Dennard Scaling and the continuance of Moore’s law has provided us with shrinking chip dimensions and higher on-chip transistor density at the cost of increas- ing power density. Chips today are highly power-constrained and often operate close to their melt-down energy thresholds. To avert the thermal meltdown of chip, designers use intelligent power-gating techniques. Here, the mode of operation is to power-up only a sub- set of IP blocks at a time. In addition to the power-density problem, decreasing transistor size has lead to decreasing silicon reliability which has led to increasing instances of on- chip faults. Both these effects lead to irregular on-chip topologies that change at runtime. Chip designers and architects today face the problem of routing packets over a dynamically changing irregular topology without sacrificing performance and more importantly without running into routing deadlocks. Another trend in the semi-conductor industry that has contibuted to the significance of this problem is the increasing use of heterogenous System-on-Chip (SoC). SoCs in most instances are tailored to the application needs. To maximise performance, these SoCs em- ploy custom-built irregular topologies to connect IP blocks. SoC designers have to to run a large number of simulations to understand the network traffic flows of the application it is being designed for. These simulation studies are carried out to ensure the absence of rout- ing deadlocks. This leads to increase in design time and consequently the time to market, leading to increase in costs and decrease in profits. Prior works in power-gating, resiliency and SoC design domains have addressed the routing deadlock problem by constructing a spanning-tree over the irregular topology and using it either as a deadlock avoidance mechanism (spanning-tree based routing) or as a deadlock-recovery mechanism (escape-vc) to route packets. However, this spanning-tree xi based solutions leads to significant loss in throughput and performance as shown in this work. In addition, a new spanning-tree construction is required every time the topology changes due to a fault in or power-gating of a network element. In this work, a new deadlock recovery framework called Static Bubble is proposed to achieve deadlock freedom in a static or dynamically changing irregular on-chip topology that doesn’t require any tree construction and thus is able to eliminate any overhead or limitations associated with the spanning-tree based solutions. Compared to the other state of the art works, static bubble provides upto 30% less latency, 4x more throughput and 50% less network EDP at less than 1% hardware overhead | |
| dc.description.degree | M.S. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/58331 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | Deadlocks | |
| dc.subject | NoC | |
| dc.subject | Routing | |
| dc.subject | Computer architecture | |
| dc.subject | Dark Silicon | |
| dc.subject | Power Gating | |
| dc.subject | Resiliency | |
| dc.subject | Topology | |
| dc.title | Aniruddh Ramrakhyani Thesis | |
| dc.type | Text | |
| dc.type.genre | Thesis | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Krishna, Tushar | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | f80c3b14-cd42-456d-b440-addf20372fbc | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
| thesis.degree.level | Masters |