Title:
Aniruddh Ramrakhyani Thesis
Aniruddh Ramrakhyani Thesis
Author(s)
Ramrakhyani, Aniruddh
Advisor(s)
Krishna, Tushar
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Abstract
The demise of Dennard Scaling and the continuance of Moore’s law has provided us with shrinking chip dimensions and higher on-chip transistor density at the cost of increas- ing power density. Chips today are highly power-constrained and often operate close to their melt-down energy thresholds. To avert the thermal meltdown of chip, designers use intelligent power-gating techniques. Here, the mode of operation is to power-up only a sub- set of IP blocks at a time. In addition to the power-density problem, decreasing transistor size has lead to decreasing silicon reliability which has led to increasing instances of on- chip faults. Both these effects lead to irregular on-chip topologies that change at runtime. Chip designers and architects today face the problem of routing packets over a dynamically changing irregular topology without sacrificing performance and more importantly without running into routing deadlocks.
Another trend in the semi-conductor industry that has contibuted to the significance of this problem is the increasing use of heterogenous System-on-Chip (SoC). SoCs in most instances are tailored to the application needs. To maximise performance, these SoCs em- ploy custom-built irregular topologies to connect IP blocks. SoC designers have to to run a large number of simulations to understand the network traffic flows of the application it is being designed for. These simulation studies are carried out to ensure the absence of rout- ing deadlocks. This leads to increase in design time and consequently the time to market, leading to increase in costs and decrease in profits.
Prior works in power-gating, resiliency and SoC design domains have addressed the routing deadlock problem by constructing a spanning-tree over the irregular topology and using it either as a deadlock avoidance mechanism (spanning-tree based routing) or as a deadlock-recovery mechanism (escape-vc) to route packets. However, this spanning-tree
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based solutions leads to significant loss in throughput and performance as shown in this work. In addition, a new spanning-tree construction is required every time the topology changes due to a fault in or power-gating of a network element.
In this work, a new deadlock recovery framework called Static Bubble is proposed to achieve deadlock freedom in a static or dynamically changing irregular on-chip topology that doesn’t require any tree construction and thus is able to eliminate any overhead or limitations associated with the spanning-tree based solutions. Compared to the other state of the art works, static bubble provides upto 30% less latency, 4x more throughput and 50% less network EDP at less than 1% hardware overhead
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Date Issued
2017-04-26
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