Title:
Bridging the gap for hardware transactional memory
Bridging the gap for hardware transactional memory
| dc.contributor.advisor | Prvulovic, Milos | |
| dc.contributor.author | Park, Sunjae Young | |
| dc.contributor.committeeMember | Kim, Hyesoon | |
| dc.contributor.committeeMember | Pande, Santosh | |
| dc.contributor.committeeMember | Qureshi, Moinuddin | |
| dc.contributor.committeeMember | Hughes, Christopher J. | |
| dc.contributor.department | Computer Science | |
| dc.date.accessioned | 2020-01-14T14:42:52Z | |
| dc.date.available | 2020-01-14T14:42:52Z | |
| dc.date.created | 2018-12 | |
| dc.date.issued | 2018-10-31 | |
| dc.date.submitted | December 2018 | |
| dc.date.updated | 2020-01-14T14:42:52Z | |
| dc.description.abstract | Transactional memory (TM) is a promising new tool for shared memory application development. Unlike mutual exclusion locks, TM allows atomic sections to execute concurrently, optimistically predicting the threads will not conflict. Commercial releases of hardware TM (HTM) brings this functionality to the mainstream. However, the commercial implementations work to provide TM functionality with the minimum amount of hardware changes required, unlike research prototypes that can work from a clean slate. As a result, there are significant gaps in performance of the commercial implementations compared to those proposed by the research community. In this thesis, I propose to several ideas that keep with this mindset, but still close the gap in performance. First, I introduce plea bits that can be used to provide enhanced conflict resolution policies, compared to the basic "requester-wins" policy used in commercial HTM implementations. Second, I propose calling a pre-abort handler instead of doing automatic state rollback when encountering abort-causing conditions. Last, I propose to change how speculative writes are handled within the transaction, allowing for lazy conflict detection. Using these techniques, I show that it is possible to support more sophisticated HTM functionality while keeping the required changes minimal. | |
| dc.description.degree | Ph.D. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/62218 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | Transactional memory | |
| dc.subject | Multithread | |
| dc.subject | Multicore | |
| dc.title | Bridging the gap for hardware transactional memory | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Prvulovic, Milos | |
| local.contributor.corporatename | College of Computing | |
| local.contributor.corporatename | School of Computer Science | |
| relation.isAdvisorOfPublication | 2d678067-bb81-43c7-be94-bd87bced736e | |
| relation.isOrgUnitOfPublication | c8892b3c-8db6-4b7b-a33a-1b67f7db2021 | |
| relation.isOrgUnitOfPublication | 6b42174a-e0e1-40e3-a581-47bed0470a1e | |
| thesis.degree.level | Doctoral |