Title:
Through-silicon-via-aware prediction and physical design for multi-granularity 3D integrated circuits

dc.contributor.advisor Lim, Sung Kyu
dc.contributor.author Kim, Dae Hyun en_US
dc.contributor.committeeMember Bakir, Muhannad
dc.contributor.committeeMember Kim, Hyesoon
dc.contributor.committeeMember Lee, Hsien-Hsin Sean
dc.contributor.committeeMember Mukhopadhyay, Saibal
dc.contributor.department Electrical and Computer Engineering en_US
dc.date.accessioned 2012-06-06T16:43:03Z
dc.date.available 2012-06-06T16:43:03Z
dc.date.issued 2012-03-27 en_US
dc.description.abstract The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs. en_US
dc.description.degree PhD en_US
dc.identifier.uri http://hdl.handle.net/1853/43642
dc.publisher Georgia Institute of Technology en_US
dc.subject 3D IC en_US
dc.subject TSV en_US
dc.subject Through-silicon via en_US
dc.subject Interconnect en_US
dc.subject Prediction en_US
dc.subject Placement en_US
dc.subject Routing en_US
dc.subject CAD en_US
dc.subject.lcsh Integrated circuits
dc.subject.lcsh Interconnects (Integrated circuit technology)
dc.title Through-silicon-via-aware prediction and physical design for multi-granularity 3D integrated circuits en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.advisor Lim, Sung Kyu
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
relation.isAdvisorOfPublication 31bc3e86-9942-4b3f-aeae-783bb95052ff
relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
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